KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 29

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851-16MLLJ does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted
by the KSZ8851-16MLLJ. It is treated transparently as data both for transmit operations.
Frame Transmitting Path Operation in TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851-16MLLJ with
generic bus interface. User can use the default value for most of the transmit registers. The following Table 8 describes all
registers which need to be set and used for transmitting single or multiple frames.
March 2010
Bit
15-11
10-0
Micrel, Inc.
Register Name
[bit](offset)
TXCR[3:0](0x70)
TXCR[8:5](0x70)
TXMIR[12:0](0x78)
TXQCR[0](0x80)
TXQCR[1](0x80)
TXQCR[2](0x80)
RXQCR[3](0x82)
TXFDPR[14](0x84)
IER[14][6](0x90)
ISR[15:0](0x92)
TXNTFSR[15:0](0x9E)
Description
Reserved.
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory for better
utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this field. Writing a 0
value to this field is not permitted.
Description
Set transmit control function as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
The amount of free transmit memory available is represented in units of byte. The TXQ memory (6
KByte) is used for both frame payload and control word.
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851-16MLLJ will enable
current TX frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a
time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit
to be cleared before setting up another new TX frame.
When this bit is written as 1, the KSZ8851-16MLLJ will generate interrupt (bit 6 in ISR register) to CPU
when TXQ memory is available based upon the total amount of TXQ space requested by CPU at
TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit
to be cleared before set to 1 again
For multiple frames to transmit, set this bit 2 = 1 (auto-enqueue). the KSZ8851-16MLLJ will enable
current all TX frames prepared in the TX buffer are queued to transmit automatically.
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame)
Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to
the data register.
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit frames size in double-word count.
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
Table 8. Registers Setting for Transmit Function Block
Table 7. Transmit Byte Count Format
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KSZ8851-16MLLJ