KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 73
KSZ8851-16MLLJ_10
Manufacturer Part Number
KSZ8851-16MLLJ_10
Description
Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
1.KSZ8851-16MLLJ_10.pdf
(90 pages)
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PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR
This register contains the PHY ID (high) for the chip.
PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR
This register contains the auto-negotiation advertisement for the PHY function.
March 2010
Micrel, Inc.
Bit
15-0
Bit
15
14
13
12-11
10
9
8
7
6
5
4-0
Default
0x0022
Default
0
0
0
0x0
1
0
1
1
1
1
0x01
R/W
RO
R/W
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RO
Description
PHYID High
High order PHYID bits.
Description
Next page
Not supported.
Reserved
Remote fault
Not supported.
Reserved
Pause (flow control capability)
1 = advertise pause capability.
0 = do not advertise pause capability.
Reserved.
Adv 100 Full
1 = advertise 100 full-duplex capability.
0 = do not advertise 100 full-duplex capability
Adv 100 Half
1= advertise 100 half-duplex capability.
0 = do not advertise 100 half-duplex capability.
Adv 10 Full
1 = advertise 10 full-duplex capability.
0 = do not advertise 10 full-duplex capability.
Adv 10 Half
1 = advertise 10 half-duplex capability.
0 = do not advertise 10 half-duplex capability.
Selector Field
802.3
73
Bit is same as:
Bit 4 in P1CR
Bit 3 in P1CR
Bit 2 in P1CR
Bit 1 in P1CR
Bit 0 in P1CR
M9999-030210-1.0
KSZ8851-16MLLJ
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