KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 45

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Register Map: MAC, PHY and QMU
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
WO = Write only.
RW = Read/Write.
W1C = Write 1 to Clear (writing an “1” to clear this bit).
0x00 – 0x07: Reserved
Chip Configuration Register (0x08 – 0x09): CCR
This register indicates the chip configuration mode based on strapping and bonding options.
0x0A – 0x0F: Reserved
March 2010
Micrel, Inc.
Bit
15-11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
0
-
-
0
-
0
0
-
0
Default Value
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Reserved.
Bus Endian mode
The EESK (pin 10) value is latched into this bit druing power-up/reset.
0: Bus in Big Endian mode, 1: Bus in Little Endian mode.
EEPROM presence
The EED_IO (pin 9) value is latched into this bit druing power-up/reset.
0: No external EEPROM, 1: Use external EEPROM.
Reserved.
8-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 8-bit bus mode operation, 1: In 8-bit bus mode operation.
16-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 16-bit bus mode operation, 1: In 16-bit bus mode operation.
Reserved.
Shared data bus mode for data and address
0: Data and address bus are seperated.
1: Data and address bus are shared.
Reserved.
Reserved.
48-Pin Chip Package
To indicate chip package is 48-pin.
0: No, 1: Yes.
Reserved.
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M9999-030210-1.0
KSZ8851-16MLLJ