KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 67

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR
This register is used to control the flow control for low watermark in QMU RX queue.
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR
This register is used to control the flow control for high watermark in QMU RX queue.
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR
This register is used to control the flow control for overrun watermark in QMU RX queue
0xB6 – 0xBF: Reserved
Chip ID and Enable Register (0xC0 – 0xC1): CIDER
This register contains the chip ID and the chip enable bit.
0xC2 – 0xC5: Reserved
March 2010
Micrel, Inc.
Bit
15-12
11-0
Bit
15-12
11-0
Bit
15-12
11-0
Bit
15-8
7-4
3-1
0
-
-
-
0x0040
0x0
Default Value
0x0500
Default Value
0x0300
Default Value
Default
0x88
0x7
0x1
R/W
RW
RW
R/W
RW
RW
R/W
RW
RW
R/W
RO
RO
RO
RW
Description
Reserved
FCLWC Flow Control Low Watermark Configuration
These bits are used to define the QMU RX queue low watermark configuration. It is in
double words count and default is 5.12 KByte available buffer space out of 12 KByte.
Description
Reserved
FCHWC Flow Control High Watermark Configuration
These bits are used to define the QMU RX queue high watermark configuration. It is in
double words count and default is 3.072 K Byte available buffer space out of 12 KByte.
Description
Reserved
FCLWC Flow Control Overrun Watermark Configuration
These bits are used to define the QMU RX queue overrun watermark configuration. It is in
double words count and default is 256 Bytes available buffer space out of 12 Kbyte.
Description
Family ID
Chip family ID
Chip ID
0x7 is assigned to KSZ8851-16MLLJ
Revision ID
Reserved
67
M9999-030210-1.0
KSZ8851-16MLLJ