KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 34

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

March 2010
Register Name[bit](offset)
Micrel, Inc.
RXFHBCR[11:0](0x7E)
RXDBCTR[15:0](0x8E)
RXFHSR[15:0](0x7C)
RXDTTR[15:0](0x8C)
RXFCTR[15:8](0x9C)
RXQCR[12:3](0x82)
RXFCTR[7:0](0x9C)
RXFDPR[14](0x86)
ISR[15:0](0x92)
RXCR1(0x74)
RXCR2(0x76)
IER[13](0x90)
Description
Set receive control function as below:
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in the Table 3.
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame). Set bit 4 to automatically enable RXQ frame buffer dequeue. Set bit 5 to enable RX frame count
threshold and read bit 10 for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12 for status. Set bit 9 enable
RX IP header two-byte offset.
To program received frame duration timer value. When Rx frame duration in RXQ exceeds this
threshold in 1uS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851-16MLLJ will
generate RX interrupt in ISR[13] and indicate the status in RXQCR[12].
To program received data byte count value. When the number of received bytes in RXQ exceeds this
threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851-16MLLJ will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[11].
Rx frame count read only. To indicate the total received frame in RXQ frame buffer when receive
interrupt (bit 13 in ISR) occurred.
To program received frame count value. When the number of received frames in RXQ exceeds this
threshold value and bit 5 of RXQCR register is set to 1, the KSZ8851-16MLLJ will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[10].
This register (read only) indicates the current received frame header status information.
This register (read only) indicates the current received frame header byte count information.
Set bit 14 to enable RXQ address register increments automatically on accesses to the data register.
Set bit 13 to enable receive interrupt in Interrupt Enable Register.
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
Table 10. Registers Setting for Receive Function Block
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KSZ8851-16MLLJ