KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 65

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Interrupt Status Register (0x92 – 0x93): ISR (Continued)
0x94 – 0x9B: Reserved
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
March 2010
Micrel, Inc.
Bit
5
4
3
2
1
0
Bit
15-8
7-0
Bit
15-0
0x0
0x0
0x0
0x0
0x0
0x0
Default Value
Default Value
0x00
0x00
Default Value
0x0000
R/W
RO
RO
RO
RO
RO
RO
R/W
RO
RW
R/W
RW
Description
RXWFDIS Receive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
Write “1000” to PMECR[5:2] to clear this bit
RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has occurred.
Write “0100” to PMECR[5:2] to clear this bit.
LDIS Linkup Detect Interrupt Status
When this bit is set, it indicates that wake-up from linkup detect status has occurred. Write
“0010” to PMECR[5:2] to clear this bit.
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
Reserved.
Reserved
Description
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1 in
ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read the
updated receive frame header information in RXFHSR/RXFHBCR registers after read this
RX frame count register.
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
When bit 5 set to 1 in RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13 in
ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this
register.
Description
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required
for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851-
16MLLJ will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is
available based upon the total amount of TXQ space requested by CPU at this register.
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M9999-030210-1.0
KSZ8851-16MLLJ