KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 70

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Power Management Event Control Register (0xD4 – 0xD5): PMECR (Continued)
Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR
This register contains the value which is used to control minimum Go-Sleep time period when the device from normal
power state to low power state or to control minimum Wake-Up time period when the device from low power state to
normal power state in energy detect mode.
PHY Reset Register (0xD8 – 0xD9): PHYRR
This register contains a control bit to reset PHY block when write an “1”.
0xDA – 0xDF: Reserved
0xE0 – 0xE3: Reserved
March 2010
Micrel, Inc.
Bit
5-2
1-0
Bit
15-8
7-0
Bit
15-1
0
Default Value
0x0
0x0
-
0
Default
0x08
0x0C
Default
R/W
RW
WO
(Self clear)
R/W
RO
(W1C)
RW
R/W
RW
RW
Description
Wake-Up Event Indication
These four bits are used to indicate the KSZ8851-16MLLJ wake-up event status as below:
0000: No wake-up event.
0001: Wake-up from energy event detected. (Bit 2 also set to 1 in ISR register)
0010: Wake-up from link up event detected. (Bit 3 also set to 1 in ISR register)
0100: Wake-up from magic packet event detected.
1000: Wake-up from wakeup frame event detected.
If Wake-on-LAN to PME Output Enable bit[11:8] are set, the KSZ8851-16MLLJ also
asserts the PME pin. These bits are cleared on power up reset or by write 1. It is not
modified by either hardware or software reset. When these bits are cleared, the KSZ8851-
16MLLJ deasserts the PME pin.
Power Management Mode
These two bits are used to control the KSZ8851-16MLLJ power management mode as
below:
00: Normal Operation Mode.
01: Energy Detect Mode. (two states in this mode either low power or normal power)
10: Soft Power Down Mode.
11: Power Saving Mode.
In energy detect mode under low power state, it can wake-up to normal operation mode
either from line or host wake-up (host CPU issues a read cycle to GRR register).
In soft power down mode, it can wake-up to normal operation mode only from host wake-
up (host CPU issues a read cycle to GRR register).
Description
Wake-up Time
This value is used to control the minimum period that the energy has to be detected
consecutively before the device is waked-up from the low power state. The unit is 16 ms
+/- 80%, the default wake-up time is 128 ms (16ms x 8). Zero time (0x00) is not allowed
Go-sleep Time
This value is used to control the minimum period that the no energy event has to be
detected consecutively before the device enters the low power state when the energy
detect mode is on. The unit is 1 sec +/-80%, the default go-sleep time is 12 sec (1s x 12).
Zero time (0x00) is not allowed
Description
Reserved.
PHY Reset Bit
This bit is write only and self clear after write an “1”, it is used to reset PHY block circuitry.
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KSZ8851-16MLLJ