MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 161
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MC68HC908JK3
Manufacturer Part Number
MC68HC908JK3
Description
MC68HC908JK1
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3.pdf
(210 pages)
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13.4.1 IRQ1 Pin
MC68H(R)C908JL3
MOTOROLA
Addr.
$001D
IRQPUD
IRQ Status and Control
IRQ1
Register Name
DECODER
NOTE:
VECTOR
RESET
FETCH
ACK1
V
I
PULLUP
DEVICE
DD
NTERNAL
—
(INTSCR)
Register
Rev. 1.0
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt
Exception Control
A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1
latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear IRQ1:
Reset:
Read:
Write:
Figure 13-2. IRQ I/O Register Summary
V
MODE1
DD
D
CK
Bit 7
IRQ1
CLR
0
0
FF
Q
External Interrupt (IRQ)
Figure 13-1. IRQ Module Block Diagram
= Unimplemented
6
0
0
.)
5
0
0
IMASK1
SYNCHRO-
VOLTAGE
DETECT
NIZER
4
0
0
HIGH
IRQF1
3
0
requests.(See 7.6
ACK1
IRQF1
2
0
0
External Interrupt (IRQ)
Functional Description
IMASK1
1
0
Technical Data
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ1
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
MODE1
Bit 0
0
161