MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 83
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MC68HC908JK3
Manufacturer Part Number
MC68HC908JK3
Description
MC68HC908JK1
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3.pdf
(210 pages)
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7.6.1.1 Hardware Interrupts
MC68H(R)C908JL3
MOTOROLA
INTERRUPT
INTERRUPT
MODULE
MODULE
I BIT
I BIT
R/W
R/W
IDB
IDB
IAB
IAB
—
DUMMY
Rev. 1.0
DUMMY
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
7-10
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
shows interrupt recovery timing.
CCR
Figure 7-10. Interrupt Recovery
SP – 1
SP – 3
Figure 7-9
System Integration Module (SIM)
A
SP – 2
SP – 2
.
X
Interrupt Entry
X
SP – 3
Figure 7-9
SP – 1
PC – 1[7:0] PC – 1[15:8] OPCODE
A
SP – 4
SP
shows interrupt entry timing.
CCR
VECT H
PC
V DATA H
System Integration Module (SIM)
VECT L
PC + 1
V DATA L
OPERAND
START ADDR
Exception Control
OPCODE
Technical Data
Figure
83