MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 110

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Monitor ROM (MON)
9.4.1 Entering Monitor Mode
Technical Data
110
Notes:
V
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using V
2. See
3. For IRQ1 = V
4. For IRQ1 = V
V
DD
The OSC1 clock must be 50% duty cycle for this condition.
MC68HRC908JL3E/JK3E/JK1E — clock must be EXT OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
MC68HRC908JL3E/JK3E/JK1E — clock must be RC OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
DD
V
V
+ V
DD
DD
+ V
Table 18-4
HI
HI
(2)
DD
DD
(contain
BLANK
BLANK
:
$FF)
NOT
for V
+ V
Table 9-1. Monitor Mode Entry Requirements and Options
X
X
HI
DD
:
+ V
Table 9-1
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
X
X
0
1
HI
1. If IRQ1 = V
2. If IRQ1 = V
3. If $FFFE & $FFFF is blank (contains $FF):
voltage level requirements.
X
X
0
0
– Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL)
– PTB3 = low
– Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL)
– PTB3 = high
– Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC)
– IRQ1 = V
X
X
1
1
shows the pin conditions for entering monitor mode. As
X
1
1
1
Monitor ROM (MON)
OSC1 Frequency
DD
DD
DD
4.9152MHz
9.8304MHz
9.8304MHz
At desired
frequency
+ V
+ V
HI
HI
:
:
DD
+ V
MC68H(R)C908JL3E/JK3E/JK1E
Frequency
2.4576MHz
(OSC1 ÷ 2)
2.4576MHz
(OSC1 ÷ 4)
2.4576MHz
(OSC1 ÷ 4)
OSC1 ÷ 4
HI
Bus
for monitor mode entry.
High-voltage entry to
monitor mode.
9600 baud communication
on PTB0. COP disabled.
Low-voltage entry to
monitor mode.
9600 baud communication
on PTB0. COP disabled.
Enters User mode.
Comments
(3)
(4)
MOTOROLA
—
Rev. 2.0