MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 164

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Input/Output (I/O) Ports
12.5.3 Port D Control Register (PDCR)
Technical Data
164
Address:
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port D pins.
The port D control register enables/disables the pull-up resistor and
slow-edge high current capability of pins PTD6 and PTD7.
SLOWDx — Slow Edge Enable
PTDPUx — Pull-up Enable
Notes:
Reset:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Read:
Write:
DDRD
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain,
high current output (25mA sink) of port pins PTD6 and PTD7
respectively. DDRDx bit is not affected by SLOWDx.
The PTDPU6 and PTDPU7 bits enable the 5kΩ pull-up on PTD6 and
PTD7 respectively, regardless the status of DDRDx bit.
Bit
0
1
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
1 = Enable 5kΩ pull-up
0 = Disable 5kΩ pull-up
$000A
Bit 7
0
0
Figure 12-12. Port D Control Register (PDCR)
PTD Bit
Input/Output (I/O) Ports
X
X
(1)
6
0
0
Table 12-4. Port D Pin Functions
Input, Hi-Z
I/O Pin
Output
Mode
5
0
0
(2)
Table 12-4
4
0
0
MC68H(R)C908JL3E/JK3E/JK1E
Read/Write
DDRD[7:0]
DDRD[7:0]
Accesses
to DDRD
SLOWD7 SLOWD6 PTDPU7
3
0
summarizes the operation
2
0
Read
Accesses to PTD
Pin
Pin
1
0
MOTOROLA
PTD[7:0]
PTD[7:0]
—
Write
PTDPU6
Rev. 2.0
Bit 0
0
(3)