MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 134
MC68HC908JK3EMP
Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3EMP.pdf
(226 pages)
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Timer Interface Module (TIM)
10.10.1 TIM Status and Control Register (TSC)
Technical Data
134
Address:
The TIM status and control register does the following:
TOF — TIM Overflow Flag Bit
TOIE — TIM Overflow Interrupt Enable Bit
Reset:
Read:
Write:
•
•
•
•
•
This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic zero to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic zero to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
one to TOF has no effect.
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Figure 10-4. TIM Status and Control Register (TSC)
$0020
Bit 7
TOF
0
0
Timer Interface Module (TIM)
= Unimplemented
TOIE
6
0
TSTOP
5
1
TRST
4
0
0
MC68H(R)C908JL3E/JK3E/JK1E
3
0
0
PS2
2
0
PS1
1
0
MOTOROLA
—
Rev. 2.0
Bit 0
PS0
0
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