MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 183

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

15.5 COP Control Register
15.6 Interrupts
15.7 Monitor Mode
15.8 Low-Power Modes
15.8.1 Wait Mode
MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
Address:
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
IRQ1 pin or on the RST pin.
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
Reset:
Read:
Write:
—
Rev. 2.0
$FFFF
Computer Operating Properly (COP)
Bit 7
Figure 15-3. COP Control Register (COPCTL)
6
5
Low byte of reset vector
Unaffected by reset
Clear COP counter
4
Computer Operating Properly (COP)
3
DD
+ V
2
HI
COP Control Register
is present on the
1
Technical Data
Bit 0
183