MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 89

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.6.1.1 Hardware Interrupts
MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
INTERRUPT
INTERRUPT
MODULE
MODULE
I BIT
I BIT
R/W
R/W
IDB
IDB
IAB
IAB
DUMMY
DUMMY
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 7-10
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
—
CCR
Rev. 2.0
Figure 7-10. Interrupt Recovery
SP – 1
SP – 3
Figure 7-9
System Integration Module (SIM)
shows interrupt recovery timing.
A
SP – 2
SP – 2
.
X
Interrupt Entry
X
SP – 3
SP – 1
Figure 7-9
PC – 1[15:8] PC – 1[7:0] OPCODE
A
SP – 4
SP
CCR
shows interrupt entry timing.
VECT H
PC
V DATA H
System Integration Module (SIM)
VECT L
PC + 1
V DATA L
OPERAND
START ADDR
Exception Control
OPCODE
Technical Data
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