HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 168

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
5.5
5.5.1
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared.
Figure 5.9 shows and example in which the CMIEA bit in 8-bit timer TCR is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev.3.00 Mar. 26, 2007 Page 126 of 772
REJ09B0355-0300
Internal
address bus
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Usage Notes
Contention between Interrupt Generation and Disabling
Figure 5.9 Contention between Interrupt Generation and Disabling
TCR write cycle by CPU
TCR address
CMIA exception handling