HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 554

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 A/D Converter
14.3
ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte
value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADDR. always read the upper byte before the lower byte. It is possible to read only
the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 14.2 shows the data flow for ADDR access.
Rev.3.00 Mar. 26, 2007 Page 512 of 772
REJ09B0355-0300
Upper byte read
Bus master
(H'AA)
Lower byte read
Bus master
(H'40)
Interface to Bus Master
Figure 14.2 ADDR Access Operation (Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
ADDRnL
ADDRnL
(H'40)
(H'40)
TEMP
TEMP
(H'40)
(H'40)
Module data bus
Module data bus
(n = A to D)
(n = A to D)