HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 183
HD6412240
Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412240.pdf
(818 pages)
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6.2.4
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 7
ICIS1
0
1
Bit 6
ICIS0
0
1
Bit
Initial value
R/W
Bus Control Register H (BCRH)
Description
Idle cycle not inserted in case of successive external read cycles in different areas.
Idle cycle inserted in case of successive external read cycles in different areas.
Description
Idle cycle not inserted in case of successive external read and external write cycles.
Idle cycle inserted in case of successive external read and external write cycles.
:
:
:
ICIS1
R/W
7
1
ICIS0
R/W
6
1
BRSTRM
R/W
5
0
BRSTS1
R/W
4
1
Rev.3.00 Mar. 26, 2007 Page 141 of 772
BRSTS0
R/W
3
0
(R/W)
—
2
0
Section 6 Bus Controller
(R/W)
REJ09B0355-0300
—
1
0
(Initial value)
(Initial value)
(R/W)
—
0
0
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