HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 509

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Restrictions Concerning DTC Updating
Operation in Case of Mode Transition
When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 clock cycles after TDR is updated by the CPU and DTC. Misoperation
may occur if the transmit clock is input within 4 clocks after TDR is updated. (Figure 12.22)
When RDR is read by the DTC, be sure to set the activation source to the relevant SCI
reception end interrupt (RXI).
The flag is cleared only when DISEL in DTC is 0 with the transfer counter not being 0. When
DISEL is 1,or DISEL is 0 with the transfer counter being 0, the flag should be cleared by CPU.
Note that transmitting, in particular, may not successfully be executed unless the TDRE flag is
cleared by CPU.
Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin
states in module stop mode or software standby mode depend on the port settings, and
becomes high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started by
setting TE to 1 again, and performing the following sequence: SSR read
TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode,
the procedure must be started again from initialization. Figure 12.23 shows a sample flowchart
for mode transition during transmission. Port pin states are shown in figures 12.24 and 12.25.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop mode or software standby mode
SCK
TDRE
Serial data
Note: When operating on an external clock, set t >4 clocks.
Figure 12.22 Example of Clocked Synchronous Transmission by DTC
t
LSB
D0
D1
D2
Section 12 Serial Communication Interface (SCI)
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Rev.3.00 Mar. 26, 2007 Page 467 of 772
D4
D5
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TDR write
REJ09B0355-0300
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