HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 33

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.9
6.10 Resets and the Bus Controller ........................................................................................... 176
Section 7 Data Transfer Controller
7.1
7.2
7.3
7.4
7.5
Section 8 I/O Ports
8.1
6.8.5
Bus Arbitration.................................................................................................................. 175
6.9.1
6.9.2
6.9.3
6.9.4
Overview........................................................................................................................... 177
7.1.1
7.1.2
7.1.3
Register Descriptions ........................................................................................................ 180
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
Operation........................................................................................................................... 187
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Number of DTC Execution States........................................................................ 201
7.3.11 Procedures for Using DTC................................................................................... 203
7.3.12 Examples of Use of the DTC ............................................................................... 204
Interrupts ........................................................................................................................... 206
Usage Notes ...................................................................................................................... 206
Overview........................................................................................................................... 207
Usage Note........................................................................................................... 175
Overview.............................................................................................................. 175
Operation ............................................................................................................. 175
Bus Transfer Timing ............................................................................................ 176
External Bus Release Usage Note........................................................................ 176
Features................................................................................................................ 177
Block Diagram ..................................................................................................... 178
Register Configuration......................................................................................... 179
DTC Mode Register A (MRA) ............................................................................ 180
DTC Mode Register B (MRB)............................................................................. 182
DTC Source Address Register (SAR).................................................................. 183
DTC Destination Address Register (DAR) .......................................................... 183
DTC Transfer Count Register A (CRA) .............................................................. 184
DTC Transfer Count Register B (CRB)............................................................... 184
DTC Enable Registers (DTCER) ......................................................................... 185
DTC Vector Register (DTVECR) ........................................................................ 186
Module Stop Control Register (MSTPCR) .......................................................... 187
Overview.............................................................................................................. 187
Activation Sources ............................................................................................... 189
DTC Vector Table................................................................................................ 191
Location of Register Information in Address Space ............................................ 194
Normal Mode....................................................................................................... 195
Repeat Mode ........................................................................................................ 196
Block Transfer Mode ........................................................................................... 197
Chain Transfer ..................................................................................................... 199
Operation Timing................................................................................................. 200
.............................................................................................................. 207
................................................................................. 177
Rev.3.00 Mar. 26, 2007 Page xxxiii of xlii
REJ09B0355-0300