HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 722

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix B Register Field
SSR0—Serial Status Register 0
Rev.3.00 Mar. 26, 2007 Page 680 of 772
REJ09B0355-0300
Bit
Initial value
Read/Write
Notes: 1. Can only be written with 0 for flag clearing.
Transmit Data Register Empty
0
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC *
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
:
:
:
2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.
R/(W) *
TDRE
7
1
Receive Data Register Full
0
1
1
R/(W) *
RDRF
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC *
[Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
6
0
2
is activated by a TXI interrupt and write data to TDR
Overrun Error
0
1
1
R/(W) *
ORER
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while
RDRF = 1
5
0
Framing Error
0
1
1
2
R/(W) *
is activated by an RXI interrupt and read data from RDR
[Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0
FER
4
0
Parity Error
0
1
1
R/(W) *
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
PER
3
0
Transmit End
1
0
1
TEND
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC *
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte
R
2
1
serial transmit character
Multiprocessor Bit
0
1
MPB
H'FF7C
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
R
1
0
Multiprocessor Bit Transfer
0
1
2
MPBT
R/W
is activated by a TXI interrupt and write data to TDR
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
SCI0