HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 104

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller (INTC)
Rev. 7.00 Jan 31, 2006 page 78 of 658
REJ09B0272-0700
I3 to I0: Interrupt mask bits of status register
Notes: 1. IRQOUT is the same signal as the interrupt request signal to the CPU (figure 5.1). The
Copy level of accep-
Push SR onto stack
Push PC onto stack
Branch to exception
tance from I3 to I0
handling routine
IRQOUT low
IRQOUT high
Read exception
execution state
2. If the accepted interrupt is edge-sensed, the IRQOUT pin returns to the high level when
vector table
Interrupt?
Program
NMI?
IRQOUT pin returns to the high level when the interrupt controller has accepted the
interrupt of a level higher than that specified by bits I3 to I0 in the CPU's status register.
the instruction to be executed by the CPU is replaced by interrupt exception handling
(before the status register is saved to the stack ). If the interrupt controller has accepted
another interrupt of a level higher than the current interrupt, and has sent an interrupt
request to the CPU, however, the IRQOUT pin remains low.
Yes
Yes
*1
*2
User break?
No
No
Figure 5.2 Flowchart of Interrupt Operation
Yes
Yes
interrupt?
level 14?
I3 to I0
Level 15
No
Yes
No
Yes
No
interrupt?
level 13?
I3 to I0
Level 14
No
Yes
Yes
No
interrupt?
I3 to I0 =
Level 1
level 0?
Yes
No
No