HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 238

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HD6417034B

Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 9 Direct Memory Access Controller (DMAC)
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States + 1 Wait State)
Rev. 7.00 Jan 31, 2006 page 212 of 658
REJ09B0272-0700
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = DRAM Bus Cycle
Figure 9.18 DREQ
Figure 9.19 DREQ
Bus cycle
Bus cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
DREQ
DACK
DREQ
DACK
CK
CK
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
CPU
CPU
CPU
CPU
(Long Pitch Normal Mode))
CPU
CPU
Tp
T1
DMAC
DMAC (R)
Tr
Tw
Tc
Tc
T2
T1
CPU
DMAC (W)
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
Tw
Tp
T2
DMAC
Tr
CPU
Tc
Tc
DREQ Level
DREQ
DREQ
DREQ
DREQ
DREQ Level
CPU
CPU

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