HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 201

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

8.11.2
The following specifies the setup time, t
the CAS signal when parity data DPH and DPL are written to DRAM in long-pitch mode (early
write).
Table 8.13 Setup Time of Parity Data DPH and DPL
Item
Data setup time with respect to CAS
(for only DPH and DPL in long-pitch mode)
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the
WRH and WRL signals of this chip and used delayed writing. Normal data is also delay-written,
but this is not a problem.
8.11.3
The maximum number of states from BREQ input to bus release is:
Note: Breakdown of approx. 4.5 states:
BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying t
bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43.
Maximum number of states for which bus is not released + approx. 4.5 states
1.5 states:
1 state (min.):
1 state (max.):
1 state:
Usage Notes on Parity Data Pins DPH and DPL
Maximum Number of States from BREQ
Notes:
computer
SuperH
Micro-
WRH or WRL
1.
2.
To prevent signal racing
Negative edge latch
RAS
CAS
RD
CK
Figure 8.42 Delayed-Write Control Circuit
Until BACK output after end of bus cycle
t
t
Sampling in 1 state before end of bus cycle
BACD1
BRQS
*1
*1
DS
, of parity data DPH and DPL with respect to the fall of
D
*2
BREQ
BREQ Input to Bus Release
BREQ
Q
Q
DWRH or DWRL
Symbol
t
Rev. 7.00 Jan 31, 2006 page 175 of 658
DS
Section 8 Bus State Controller (BSC)
RAS
CAS
OE
WE
Min
-5ns
DRAM
REJ09B0272-0700
BRQS
, the