HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 431

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

3.
Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 13.20
shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure
for transmitting and receiving serial data simultaneously is listed below.
1. SCI initialization: select the TxD and RxD pin function with the PFC.
2. SCI status check and transmit data write: read the serial status register (SSR), check that the
3. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the
4. SCI status check and receive data read: read the serial status register (SSR), check that RDRF
5. To continue transmitting and receiving serial data: read the RDRF bit and RDR, and clear
not pass (receive error), the SCI operates as indicated in table 13.8. When the error flag is set
to 1 and the RDRF bit is cleared to 0, the RDRF bit will not be set to 1 during reception. When
restarting reception, be sure to clear the error flag to 0.
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to
0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1.
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to
check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0 before the
MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-data-
empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared
automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR,
the RDRF bit is cleared automatically.
After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR,
the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-
error interrupt (ERI).
Section 13 Serial Communication Interface (SCI)
Rev. 7.00 Jan 31, 2006 page 405 of 658
REJ09B0272-0700