HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 114

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 User Break Controller (UBC)
6.2.3
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
A reset initializes BBR to H'0000. It is not initialized in standby mode.
Bits 15–8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMA Cycle Select (CD1 and CD0): CD1 and CD0 select whether to
break on CPU and/or DMA bus cycles.
Bit 7: CD1
0
1
Rev. 7.00 Jan 31, 2006 page 88 of 658
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Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
CPU cycle or DMA cycle
Instruction fetch or data access
Read or write
Operand size (byte, word, longword)
Break Bus Cycle Register (BBR)
Bit 6: CD0
0
1
0
1
CD1
R/W
15
—
—
0
7
0
Description
No break interrupt occurs
Break only on CPU cycles
Break only on DMA cycles
Break on both CPU and DMA cycles
CD0
R/W
14
—
—
0
6
0
R/W
ID1
13
—
—
0
5
0
R/W
ID0
12
—
—
0
4
0
RW1
R/W
11
—
—
0
3
0
RW0
R/W
10
—
—
0
2
0
R/W
SZ1
—
—
9
0
1
0
(Initial value)
R/W
SZ0
—
—
8
0
0
0