HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 327

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

10.6.8
If an input capture signal is generated during the T3 state of a general register write cycle, the
input capture transfer takes priority and the write to GR is not performed. The timing is shown in
figure 10.65.
10.6.9
When a counter is cleared by compare match, the counter is cleared in the last state in which the
TCNT value matches the GR value (when TCNT is updated from the matching count to the next
count). The actual counter frequency is therefore given by the following formula:
Figure 10.65 Contention between General Register Write and Input Capture
f = /(N + 1)
(f: counter frequency; : operating frequency; N: value set in GR)
Note on Waveform Cycle Setting
Contention between General Register Write and Input Capture
Input capture
write signal
Address
Internal
TCNT
signal
GR
CK
T1
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
GR write cycle
GR address
T2
M
Rev. 7.00 Jan 31, 2006 page 301 of 658
T3
M
REJ09B0272-0700