NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 25

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NAND08GW3C2A

Manufacturer Part Number
NAND08GW3C2A
Description
8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet

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NAND08GW3C2A, NAND16GW3C2A
Figure 10. Random Data Input during Sequential Data Input
6.7
RB
I/O
Row Add 1,2,3
Code
Cmd
80h
Multiplane Page Program
The devices support Multiplane Page Program, that allows the programming of two pages in
parallel, one in each plane.
A Multiplane Page Program operation requires two steps:
1.
5 Add cycles
Address
The first step loads serially up to two pages of data (4224 bytes) into the data buffer. It
requires:
Inputs
Col Add 1,2
One clock cycle to set up the Page Program command (see
Sequential
Five bus write cycles to input the first page address and data. The address of the
first page must be within the first plane (A19 = 0).
One bus write cycle to issue the Page Program Confirm code. After this the device
is busy for a time of t
When the device returns to the ready state (Ready/Busy High), a Multiplane Page
Program Setup code must be issued, followed by the second page address (5
write cycles) and data. The address of the second page must be within the second
plane (A19=1), and A18 to A12 must be the address bits loaded during the first
address insertion.
Main Area
Data Intput
Input).
Spare
Code
Area
Cmd
85h
BLBH5
2 Add cycles
Address
Col Add 1,2
.
Inputs
Data Input
(Program Busy time)
tBLBH2
Confirm
Code
10h
Main Area
Busy
Read Status Register
Section 6.5:
Device operations
70h
Spare
Area
SR0
ai08664
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