NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 28

• Manufacturer Part Number: NAND08GW3C2A
• Description: 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.10
6.11
6.11.1
6.11.2
6.11.3
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Reset
The Reset command is used to reset the command interface and Status Register. If the
Reset command is issued during any operation, the operation is aborted. If it is a Program
or Erase operation that is being aborted, the contents of the memory locations being
modified are no longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for t
of t
issued. Refer to
Read Status Register
The device contains a Status Register that provides information on the current or previous
Program or Erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in Read
Status Register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle a new Read command must be issued to
continue with a Page Read operation.
Refer to
with the following text descriptions.
Write protection bit (SR7)
The write protection bit can identify if the device is protected or not. If the write protection bit
is set to ‘1’ the device is not protected and Program or Erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and Program or Erase operations are
not allowed.
P/E/R controller bit (SR6)
Status register bit SR6 acts as a P/E/R controller bit, which indicates whether the P/E/R
controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller
is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is
ready).
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ‘1’ when a Program or Erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’, the operation has completed successfully.
BLBH4
Table 8
depends on the operation that the device was performing when the command was
Table 21
which summarizes Status Register bits and should be read in conjunction
for the values.
BLBH4
after the Reset command is issued. The value
NAND08GW3C2A, NAND16GW3C2A