NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 27

• Manufacturer Part Number: NAND08GW3C2A
• Description: 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GW3C2A, NAND16GW3C2A
Figure 12. Block Erase operation
6.9
Figure 13. Multiplane Block Erase operation
RB
I/O
RB
I/O
Block Erase
Setup Code
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completes successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Multiplane Block Erase
The Multiplane Block Erase operation allows erasing two blocks in parallel, one in each
plane. It consists of three steps (refer to
1.
2.
If the Multiplane Block Erase fails, an error is signaled on bit SR0 of the status register.
However, there is no way to identify for which page the Multiplane Block Erase operation
failed.
60h
Block Erase
Setup Code
Eight bus cycles are required to set up the Block Erase command and load the
addresses of the blocks to be erased. The Setup command, followed by the address of
the block to be erased, must be issued for each block. No dummy busy time is required
between the first and second block address insertion. As for Multiplane Page Program,
the address of the first and second page must be within the first plane (A19 = 0) and
second plane (A19 = 1), respectively.
One bus cycle is then required to issue the Multiplane Block Erase confirm command
and start the P/E/R controller.
60h
Block Address
A19=0
Inputs
Block Address
Inputs
Block Erase
Setup Code
60h
Confirm
Block Address
Code
D0h
A19=1
Inputs
Figure 13: Multiplane Block Erase
Confirm
Code
D0h
(Erase Busy time)
tBLBH3
Busy
(Erase Busy time)
tBLBH3
Busy
Read Status Register
70h
Read Status Register
Device operations
operation):
70h
SR0
SR0
ai13637
ai07593
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