MCIMX6D7CVT08AC Freescale Semiconductor, MCIMX6D7CVT08AC Datasheet - Page 10

• Manufacturer Part Number: MCIMX6D7CVT08AC
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Modules List
10
Mnemonic
eCSPI1-5
DCIC-0
DCIC-1
EPIT-1
EPIT-2
Block
ENET
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
CTM
CSU
DAP
CSI
DSI
MIPI CSI-2 Interface Multimedia
Central Security Unit Security
Cross Trigger
Interfaces
Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.
Debug Access Port
Display Content
Integrity Checker
MIPI DSI interface
Configurable SPI
Ethernet Controller
Enhanced Periodic
Interrupt Timer
Block Name
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Peripherals
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from
System
Control
Peripherals
Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX
Multimedia
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Timer
Peripherals
Subsystem
The CSI IP provides MIPI CSI-2 standard camera interface port. The
CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to
800 Mbps for 4 data lanes.
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX 6Dual/6Quad platform. The Security
Control Registers (SCR) of the CSU are set during boot time by the HAB
and are locked to prevent further writing.
masters attached to CTIs. The CTI module is internal to the Cortex-A9
Core Platform.
The CTM module is internal to the Cortex-A9 Core Platform.
The DAP provides real-time access for the debugger without halting the
core to:
The DAP also provides debugger access to JTAG scan chains. The DAP
module is internal to the Cortex-A9 Core Platform.
6Dual/6Quad processor has two such modules, one for each IPU.
The MIPI DSI IP provides DSI standard display port interface. The DSI
interface support 80 Mbps to 1 Gbps speed per data lane.
Full-duplex enhanced Synchronous Serial Interface. It is configurable to
support Master/Slave modes, four chip selects to support multiple
peripherals.
The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to complete
the interface to the media. The i.MX 6Dual/6Quad processors also
consist of hardware assist for IEEE 1588 standard. For details, see the
ENET chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).
Note: The theoretical maximum performance of 1 Gbps ENET is limited
to 470 Mbps (total for Tx and Rx) due to internal bus throughput
limitations. The actual measured performance in optimized environment
is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX
6Dual/6Quad errata document (IMX6DQCE).
Each EPIT is a 32-bit “set and forget” timer that starts counting after the
EPIT is enabled by software. It is capable of providing precise interrupts
at regular intervals with minimal processor intervention. It has a 12-bit
prescaler for division of input clock frequency to get the required time
setting for the interrupts to occur, and counter value can be programmed
on the fly.
• System memory and peripheral registers
• All debug configuration registers
Brief Description
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