MCIMX6D7CVT08AC Freescale Semiconductor, MCIMX6D7CVT08AC Datasheet - Page 31

• Manufacturer Part Number: MCIMX6D7CVT08AC
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

4.2.2
No special restrictions for i.MX 6Dual/6Quad SoC.
4.2.3
4.3
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX 6Dual/6Quad reference manual
(IMX6DQRM) for details on the power tree scheme recommended operation.
4.3.1
There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because
of their construction). The advantages of the regulators are to reduce the input supply variation because of
their input supply ripple rejection and their on die trimming. This translates into more voltage for the die
producing higher operating frequencies. These regulators have three basic modes.
Freescale Semiconductor
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All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx)
is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For
information about I/O power supply of each pin, see “Power Group” column of
mm Functional Contact Assignments," on page
When the SATA interface is not used, the SATA_VP and SATA_VPH supplies should be grounded.
The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N,
SATA_PHY_RX_P, and SATA_PHY_TX_N) can be left floating. It is recommended not to turn
OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive power
consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain powered.
When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should
be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N,
PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can be left floating. It is recommended not to turn
the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive power
consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must remain
powered.
Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the
load unaltered. The analog part of the regulator is powered down in this state, removing any loss
other than the IR drop through the power grid and FET.
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
Integrated LDO Voltage Regulator Parameters
Power-Down Sequence
Power Supplies Usage
Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO or LDO bypass operation only.
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2
NOTE
141.
Electrical Characteristics
Table 92, "21 x 21
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