MCIMX6D7CVT08AC Freescale Semiconductor, MCIMX6D7CVT08AC Datasheet - Page 103

• Manufacturer Part Number: MCIMX6D7CVT08AC
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Table 66
Freescale Semiconductor
IP5
IP6
IP7
IP8
IP9
IP10
IP12
IP13
IP14
IP15
ID
Display interface clock period
Display pixel clock period
Screen width time
HSYNC width time
Horizontal blank interval 1
Horizontal blank interval 2
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
shows timing characteristics of signals presented in
Parameter
Table 66. Synchronous Display Interface Timing Characteristics (Pixel Level)
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2
Symbol
Tdpcp
Tdicp
Thbi1
Thbi2
Tvbi1
Tvbi2
Thsw
Tvsw
Tsw
Tsh
DISP_CLK_PER_PIXEL
(SCREEN_HEIGHT –
BGXP – FW)
(SCREEN_WIDTH –
(SCREEN_HEIGHT)
(SCREEN_WIDTH)
BGYP – FH)
(HSYNC_WIDTH)
VSYNC_WIDTH
BGXP
BGYP


(see

Value
Tdicp
Tdicp
Tsw


1
Tdicp
)
Tsw


Tdicp
Tsw
Figure 67
Display interface clock IPP_DISP_CLK
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n).
The DISP_CLK_PER_PIXEL is virtual
parameter to define display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
BGXP—width of a horizontal blanking
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
SCREEN_HEIGHT— screen height in lines
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
BGYP—width of first Vertical
Width of second vertical blanking interval in
line. The FH should be built by suitable DI’s
counter.
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
VSYNC_WIDTH—Vsync width in DI_CLK
blanking interval in line. The BGYP should
be built by suitable DI’s counter.
and
Figure
Description
2
.
Electrical Characteristics
68.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
103