MCIMX6D7CVT08AC Freescale Semiconductor, MCIMX6D7CVT08AC Datasheet - Page 82

• Manufacturer Part Number: MCIMX6D7CVT08AC
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
4.11.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are
identical to those shown in
4.11.5
4.11.5.1 ENET MII Mode Timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.11.5.1.1
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 46
the figure.
1
82
M1
M2
M3
M4
ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
ID
ENET_RX_DATA3,2,1,0
ENET_RX_CLK (input)
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
shows MII receive signal timings.
Ethernet Controller (ENET) AC Electrical Specifications
ENET_RX_EN
ENET_RX_ER
MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
(inputs)
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2
Table 22, "GPIO I/O DC Parameters," on page
Figure 46. MII Receive Signal Timing Diagram
Characteristic
Table 54. MII Receive Signal Timing
M1
1
Table 54
M2
M3
describes the timing parameters (M1–M4) shown in
35%
35%
Min
M4
5
5
36.
65%
Max
65%
—
—
Freescale Semiconductor
ENET_RX_CLK period
ENET_RX_CLK period
Unit
ns
ns