MCIMX6D7CVT08AC Freescale Semiconductor, MCIMX6D7CVT08AC Datasheet - Page 104

• Manufacturer Part Number: MCIMX6D7CVT08AC
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
1
2
The maximum accuracy of UP/DOWN edge of controls is:
104
IP5o
IP13o Offset of VSYNC
IP8o
IP9o
ID
Display interface clock period immediate value.
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between
HSYNCs is a SCREEN_WIDTH.
Offset of IPP_DISP_CLK
Offset of HSYNC
Offset of DRDY
Table 66. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
Tdicp
Parameter
=
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2







T diclk floor
T diclk



DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
Symbol
Todrdy
Todicp
DISP_CLK_PERIOD
--------------------------------------------------- -
Tovs
Tohs
DI_CLK_PERIOD
Tdicp
Accuracy
=
DISP_CLK_OFFSET
VSYNC_OFFSET
HSYNC_OFFSET
T diclk
DRDY_OFFSET
=
,




Value

0.5 T diclk
Tdiclk
Tdiclk
Tdiclk
Tdiclk

+
DISP_CLK_PERIOD
--------------------------------------------------- -

0.5 0.5
DI_CLK_PERIOD



 0.62ns
,

DISP_CLK_OFFSET—offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK
(0.5 DI_CLK Resolution).
Defined by DISP_CLK counter.
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK
DRDY_OFFSET—offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK
(0.5 DI_CLK Resolution). The
VSYNC_OFFSET should be built by
suitable DI’s counter.
(0.5 DI_CLK Resolution). The
HSYNC_OFFSET should be built by
suitable DI’s counter.
(0.5 DI_CLK Resolution).
The DRDY_OFFSET should be built by
suitable DI’s counter.
for fractional
for integer DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
Description


2
2
Freescale Semiconductor


2
2
Unit
ns
ns
ns
ns