MT48LC8M16A2P-75:G Micron Technology Inc, MT48LC8M16A2P-75:G Datasheet - Page 23

• Manufacturer Part Number: MT48LC8M16A2P-75:G
• Description: IC SDRAM 128MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2P-75:G

• Memory Type: SDRAM
• Format - Memory: RAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Memory Configuration: 16M X 8
• Access Time: 5.4ns
• Page Size: 128Mbit
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

BURST TERMINATE
AUTO REFRESH
SELF REFRESH
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-
sistent in that either it is enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in the “Operations”
section on page 24.
The BURST TERMINATE command is used either to truncate fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the “Operations” section on
page 24.
The BURST TERMINATE command does not precharge the row; the row will remain
open until a PRECHARGE command is issued.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in older DRAMs. This command is nonpersistent, so
it must be issued each time a refresh is required. All active banks must be PRECHARGED
prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should
not be issued until the minimum
shown in the operation section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the
128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command
every 15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the
refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO
REFRESH commands can be issued in a burst at the minimum cycle rate (
every 64ms (commercial and industrial) or 16ms (automotive).
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to
indefinite period beyond that.
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
23
t
RP has been met after the PRECHARGE command as
t
RAS and may remain in self refresh mode for an
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
Commands
t
RFC), once