MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 12
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Functional Block Diagrams
Figure 3:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
RZQ
V
SS
A[13:0]
BA[2:0]
Q
CK, CK#
ZQ
RESET#
RAS#
CAS#
WE#
ODT
CKE
A12
CS#
17
Address
register
256 Meg x 4 Functional Block Diagram
Mode registers
Control
logic
16
Refresh
counter
14
ZQCL, ZQCS
11
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
3
BC4 (burst chop)
OTF
14
address
3
Row-
MUX
Column-
counter/
control
address
14
Bank
logic
latch
ZQ CAL
decoder
address
Bank 0
latch
row-
and
Bank 1
Bank 2
8
3
Bank 3
Bank 4
16,384
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 7
(16,384 x 256 x 32)
To pull-up/pull-down
Sense amplifiers
DM mask logic
I/O gating
Column
decoder
memory
Bank 0
(x32)
8,192
networks
array
256
Bank 1
Bank 2
Bank 3
Bank 4
12
Bank 5
Bank 6
Bank 7
DM
32
BC4
OTF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
32
32
Columns 0, 1, and 2
interface
CK, CK#
READ
MUX
FIFO
data
and
Data
1Gb: x4, x8, x16 DDR3 SDRAM
Data
4
4
lower nibble for BC4)
Functional Block Diagrams
(select upper or
Column 2
WRITE
drivers
input
and
logic
control
CK, CK#
ODT
drivers
READ
BC4
DLL
©2006 Micron Technology, Inc. All rights reserved.
DQS, DQS#
DQ[3:0]
sw1
sw1
sw1
R
R
R
V
V
V
TT
TT
TT
DD
DD
DD
_
_
_
Q/2
NOM
NOM
Q/2
NOM
Q/2
R
R
R
sw2
sw2
TT
TT
sw2
TT
_
_
_
WR
WR
WR
(1, 2)
(1 . . . 4)
DQ[3:0]
DQS, DQS#
DM
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