MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 13
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 4:
Figure 5:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
RZQ
RZQ
V
V
SS
SS
BA[2:0]
A[12:0]
BA[2:0]
A[13:0]
Q
Q
ZQ
CK, CK#
CK, CK#
ZQ
RESET#
RESET#
RAS#
CAS#
RAS#
CAS#
WE#
ODT
WE#
ODT
CKE
A12
CKE
A12
CS#
CS#
16
17
Address
Address
register
register
128 Meg x 8 Functional Block Diagram
64 Meg x 16 Functional Block Diagram
Mode registers
Mode registers
Control
Control
logic
logic
16
16
13
14
counter
Refresh
counter
Refresh
ZQCL, ZQCS
ZQCL, ZQCS
10
10
3
3
BC4 (burst chop)
OTF
OTF
BC4 (burst chop)
13
14
address
3
address
3
Row-
MUX
Row-
MUX
Column-
counter/
Column-
address
counter/
control
control
address
13
Bank
latch
14
logic
Bank
logic
latch
ZQ CAL
ZQ CAL
decoder
address
Bank 0
address
decoder
row-
latch
Bank 0
and
row-
latch
and
Bank 1
Bank 1
Bank 2
Bank 2
7
3
7
3
Bank 3
Bank 3
Bank 4
Bank 4
16,384
8,192
Bank 5
Bank 5
Bank 6
Bank 6
Columns 0, 1, and 2
Columns 0, 1, and 2
Bank 7
Bank 7
To ODT/output drivers
(8192 x 128 x 128)
To ODT/output drivers
(16,384 x 128 x 64)
Sense amplifiers
Sense amplifiers
DM mask logic
DM mask logic
I/O gating
I/O gating
decoder
memory
Column
Column
decoder
memory
Bank 0
16,384
x128)
Bank 0
array
(128
8,192
(128
x64)
array
Bank 1
Bank 1
Bank 2
Bank 2
Bank 3
Bank 3
Bank 4
Bank 4
13
Bank 5
Bank 5
Bank 6
Bank 6
Bank 7
Bank 7
128
64
BC4
OTF
BC4
OTF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128
128
64
64
Columns 0, 1, and 2
Column 0, 1, and 2
interface
interface
CK, CK#
READ
CK, CK#
READ
Data
MUX
MUX
FIFO
data
FIFO
data
and
and
Data
1Gb: x4, x8, x16 DDR3 SDRAM
Data
Data
16
8
lower nibble for BC4)
16
8
lower nibble for BC4)
(select upper or
Functional Block Diagrams
(select upper or
Column 2
Column 2
WRITE
drivers
input
logic
WRITE
drivers
and
input
and
logic
control
control
ODT
ODT
CK, CK#
drivers
CK, CK#
READ
drivers
READ
DLL
BC4
DLL
BC4
©2006 Micron Technology, Inc. All rights reserved.
DQ[15:0]
LDQS, LDQS#, UDQS, UDQS#
DQ[7:0]
DQS, DQS#
sw1
sw1
sw1
sw1
sw1
sw1
R
R
R
R
V
V
R
V
R
TT
V
V
TT
TT
TT
V
DD
TT
DD
DD
TT
DD
_
DD
_
_
_
DD
_
_
Q/2
NOM
Q/2
NOM
Q/2
NOM
NOM
NOM
Q/2
Q/2
NOM
Q/2
DQ8
R
R
R
R
R
sw2
TT
sw2
sw2
sw2
R
sw2
TT
TT
sw2
TT
TT
TT
_
_
_
_
_
WR
WR
_
WR
WR
WR
WR
(1 . . . 4)
(1, 2)
(1 . . . 16)
(1 . . . 8)
(1, 2)
LDM/UDM
DQ[15:0]
LDQS, LDQS#
UDQS, UDQS#
DQ[7:0]
DQS, DQS#
DM/TDQS
(shared pin)
TDQS#
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