MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 169
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 117: Synchronous ODT (BC4)
Command
ODT
CKE
CK#
R
CK
TT
NOP
T0
NOP
T1
Notes:
NOP
T2
1. WL = 7. R
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE
5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be
command with ODT HIGH to ODT registered LOW.
satisfied from the registration of the WRITE command at T7.
ODTH4
ODTL on = WL - 2
NOP
T3
TT
NOP
T4
_
NOM
is enabled. R
NOP
T5
NOP
T6
TT
t AON (MIN)
_
t AON (MAX)
WR
WRS4
ODTL off = WL - 2
T7
is disabled.
ODTH4 (MIN)
ODTL on = WL - 2
NOP
T8
R
TT
_
NOM
ODTH4
NOP
T9
t AOF (MAX)
t AOF (MIN)
NOP
T10
NOP
T11
t AON (MIN)
t AON (MAX)
NOP
T12
ODTLoff = WL - 2
NOP
T13
R
TT
_
NOM
NOP
T14
NOP
T15
Transitioning
NOP
T16
Don’t Care
t AOF (MIN)
t AOF (MAX)
NOP
T17
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