MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 73
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 53:
Parameter
R
R
R
R
Asynchronous R
(power-down with DLL off)
Asynchronous R
(power-down with DLL off)
ODT HIGH time with WRITE command and
BL8
ODT HIGH time without WRITE command or
with WRITE command and BC4
R
R
R
R
First DQS, DQS# rising edge
DQS, DQS# delay
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
Write leveling output delay
Write leveling output error
TT
TT
TT
TT
TT
TT
TT
TT
_
_
_
synchronous turn-on delay
synchronous turn-off delay
turn-on from ODTL on reference
turn-off from ODTL off reference
dynamic change skew
NOM
WR
WR
-to-R
-to-R
-to-R
TT
TT
TT
Electrical Characteristics and AC Operating Conditions (Sheet 7 of 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
_
_
NOM
NOM
_
TT
TT
WR
turn-on delay
turn-off delay
change skew - BC4
change skew - BL8
change skew
t
ODTL
ODTL
ODTL
WLDQSEN
ODTL on
ODTL off
t
Symbol
t
t
WLMRD
AONPD
ODTH8
ODTH4
t
AOFPD
t
t
t
WLOE
t
t
t
AON
WLH
WLO
AOF
ADC
WLS
CNW
CNW
CNW
4
8
–400
Min
325
325
0.3
0.3
Write Leveling Timing
40
25
DDR3-800
Dynamic ODT Timing
0
0
ODT Timing
Max
400
0.7
0.7
–
–
–
–
9
2
–300
Min
245
245
0.3
0.3
DDR3-1066
40
25
0
0
MIN = 6; MAX = n/a
MIN = 4; MAX = n/a
MIN = 1; MAX = 9
MIN = 1; MAX = 9
CWL + AL - 2CK
CWL + AL - 2CK
4CK + ODTL off
6CK + ODTL off
Max
300
0.7
0.7
–
–
–
–
9
2
WL - 2CK
–250
Min
195
195
0.3
0.3
DDR3-1333
40
25
0
0
Max
250
0.7
0.7
9
2
–
–
–
–
–225
Min
163
163
0.3
0.3
DDR3-1600
40
25
0
0
Max
225
0.7
0.7
7.5
–
–
–
–
2
Units Notes
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
ps
ns
ns
ps
ps
ns
ns
24, 39
40, 41
39
41
39
41
40
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