MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 21
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MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 5:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Ball Assignments
N3, P7, P3, N2,
P8, P2, R8, R2,
M2, N8, M3
J3, K3, L3
T8, R3,
R7, N7
J7, K7
L7,
K9
E7
K1
L2
96-Ball FBGA – x16 Ball Descriptions
RAS#, CAS#, WE#
A0, A1, A2, A3,
A4, A5, A6, A7,
BA0, BA1, BA2
A11, A12/BC#
Symbol
CK, CK#
A10/AP,
A8, A9
LDM
ODT
CKE
CS#
Input
Input
Input
Input
Input
Input
Input
Input
Type
Description
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to V
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See
Table 62 on page 91.
Bank address inputs: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
V
Clock: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle),or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to V
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to V
Input data mask: LDM is a lower-byte, input mask signal for write
data. Lower-byte input data is masked when LDM is sampled HIGH
along with the input data during a write access. Although the LDM
ball is input-only, the LDM loading is designed to match that of the
DQ and DQS balls. LDM is referenced to V
On-die termination: ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#,
LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/
TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and
DM for the x4. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to V
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to V
REF
CA.
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
REF
CA.
REF
1Gb: x4, x8, x16 DDR3 SDRAM
CA. A12/BC#: When enabled in the
REF
©2006 Micron Technology, Inc. All rights reserved.
REF
CA.
REF
DQ.
CA.
REF
CA.