MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 174
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. F 11/08 EN
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period occurs
if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins
and it ends when CKE is first registered LOW.
1
when CKE goes LOW, power-down entry will end
rather than when CKE is first registered LOW. Power-down entry will then become the
greater of
ODT assertion during power-down entry results in an R
t
(MAX) and ODTL on ×
may result in an R
off ×
off ×
If the AL has a large value, the uncertainty of the state of R
because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL.
Figure 120 on page 175 shows three different cases:
• ODT_A: Synchronous behavior before
• ODT_B: ODT state changes during the transition period with
• ODT_C: ODT state changes after the transition period with asynchronous behavior
AONPD (MIN) and ODTL on ×
t
CK or ODTL on + 1
ODTL on ×
ODTL on ×
t
t
CK +
CK +
t
ANPD and
t
t
AOF (MIN) or as late as the greater of
AOF (MAX). Table 83 on page 175 summarizes these parameters.
t
t
CK +
CK +
TT
t
t
t
AON (MIN) and
AON (MAX)
change as early as the lesser of
CK. If a REFRESH command has been issued, and it is in progress
t
RFC - REFRESH command to CKE registered LOW.
t
CK +
t
174
AON (MAX). ODT de-assertion during power-down entry
t
CK +
t
t
AONPD (MAX) greater than
AON (MIN) or as late as the greater of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
ANPD prior to CKE first being registered LOW,
t
ANPD
t
ANPD is equal to the greater of ODTL off +
1Gb: x4, x8, x16 DDR3 SDRAM
t
t
AOFPD (MAX) and ODTL
RFC after the REFRESH command
t
AOFPD (MIN) and ODTL
On-Die Termination (ODT)
TT
TT
change as early as the lesser of
becomes quite large. This is
©2006 Micron Technology, Inc. All rights reserved.
t
AONPD (MIN) less than
t
AONPD
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