MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet - Page 114

• Manufacturer Part Number: MT41J256M8JE-15E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8JE-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 70: Truth Table – CKE
Notes 1–2 apply to the entire table; see Table 69 (page 112) for additional command details
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Current State
Power-down
Self refresh
Bank(s) active
Reading
Writing
Precharging
Refreshing
All banks idle
3
Previous Cycle
Notes:
(n - 1)
H
H
H
H
H
H
H
L
L
L
L
1. All states and sequences not shown are illegal or reserved unless explicitly described else-
2.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
5. COMMAND is the command registered at the clock edge (must be a legal command as
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all
CKE
where in this document.
t
CKE must remain at the valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of
previous clock edge.
defined in Table 69 (page 112)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.
timings from previous operations are satisfied. All self refresh exit and power-down exit
parameters are also satisfied.
4
CKE (MIN) means CKE must be registered at multiple consecutive positive clock edges.
Present Cycle
(n)
H
H
L
L
L
L
L
L
L
L
L
4
(RAS#, CAS#, WE#, CS#)
114
“Don’t Care”
“Don’t Care”
Command
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
REFRESH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
5
2Gb: x4, x8, x16 DDR3 SDRAM
t
IS +
Precharge power-down entry
Precharge power-down entry
t
Active power-down entry
CKE (MIN) +
Commands – Truth Tables
Maintain power-down
Maintain self refresh
Power-down entry
Power-down entry
Power-down entry
Power-down exit
Self refresh exit
Self refresh
Action
© 2006 Micron Technology, Inc. All rights reserved.
t
IH.
5
Notes
6