MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet - Page 132

• Manufacturer Part Number: MT41J256M8JE-15E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8JE-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mode Registers
Figure 50: MRS to MRS Command Timing (
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Notes:
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or
until the device loses power.
Contents of a mode register can be altered by reexecuting the MRS command. If the
user chooses to modify only a subset of the mode register’s variables, all variables must
be programmed when the MRS command is issued. Reprogramming the mode register
will not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks are idle and in the
precharged state (
mand has been issued, two parameters must be satisfied:
ler must wait
Command
The controller must also wait
ing NOP and DES). The DRAM requires
with the exception of DLL RESET, which requires additional time. Until
satisfied, the updated features are to be assumed unavailable.
Address
1. Prior to issuing the MRS command, all banks must be idle and precharged,
2.
3. CKE must be registered HIGH from the MRS command until
4. For a CAS latency change,
CKE 3
CK#
must be satisfied, and no data bursts can be in progress.
t
Down Mode (page 179)).
CK
MRD specifies the MRS to MRS command minimum cycle time.
MRS 1
Valid
T0
t
MRD before initiating any subsequent MRS commands.
t
RP is satisfied and no data bursts are in progress). After an MRS com-
t
MRD)
NOP
T1
132
t
t
MOD before initiating any nonMRS commands (exclud-
XPDLL timing must be met before any nonMRS command.
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2
t
MOD in order to update the requested features,
t MRD
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
Ta0
Indicates A Break in
Time Scale
t
MRD and
t
MRSPDEN (MIN) (see Power-
© 2006 Micron Technology, Inc. All rights reserved.
NOP
Ta1
Mode Registers
t
MOD. The control-
t
MOD has been
t
RP (MIN)
Don’t Care
MRS 2
Valid
Ta2