MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet - Page 164

• Manufacturer Part Number: MT41J256M8JE-15E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8JE-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 79: Method for Calculating
Figure 80:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
t HZ (DQS), t HZ (DQ)
t
RPRE Timing
t HZ (DQS), t HZ (DQ) end point = 2 × T1 - T2
Notes:
CK#
Single-ended signal provided
as background information
Single-ended signal provided
as background information
Resulting differential
signal relevant for
t RPRE specification
DQS#
CK
DQS
1. Within a burst, the rising strobe edge is not necessarily fixed at
2. The DQS high pulse width is defined by
3. The minimum pulse width of the READ preamble is defined by
DQS - DQS#
(MAX). Instead, the rising strobe edge can vary between
t
strobe case) and
strobe case); however, they tend to track one another.
mum pulse width of the READ postamble is defined by
QSL. Likewise,
T1
t RPRE begins
T2
t
LZ and
T1
t C
t A
t
LZ (DQS) MIN and
V
V
V
V
t
LZ (DQS) MAX and
t
OH
OH
OL
OL
HZ
+ 2xmV
+ xmV
- xmV
- 2xmV
164
t RPRE
t
V
HZ (DQS) MIN are not tied to
V
V
TT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
V
TT
t
TT
HZ (DQS) MAX are not tied to
TT
+ 2xmV
- 2xmV
+ xmV
t LZ (DQS), t LZ (DQ) begin point = 2 × T1 - T2
- xmV
t
QSH, and the DQS low pulse width is defined by
t B
2Gb: x4, x8, x16 DDR3 SDRAM
t RPRE ends
T2
t D
T1
T2
t
t
DQSCK (MIN) and
RPST (MIN).
© 2006 Micron Technology, Inc. All rights reserved.
t LZ (DQS), t LZ (DQ)
t
t
RPRE (MIN). The mini-
DQSCK (MIN) or
t
V
V
V
0V
DQSCK (MIN) (early
TT
TT
TT
t
DQSCK (MAX) (late
t
DQSCK (MAX).
t
DQSCK