MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet - Page 15

• Manufacturer Part Number: MT41J256M8JE-15E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8JE-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4: 256 Meg x 8 Functional Block Diagram
RZQ
Figure 5: 128 Meg x 16 Functional Block Diagram
RZQ
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
V
V
SSQ
SSQ
BA[2:0]
A[14:0]
BA[2:0]
A[13:0]
ZQ
CK, CK#
CK, CK#
ZQ
RESET#
RESET#
RAS#
CAS#
RAS#
CAS#
WE#
ODT
WE#
ODT
CKE
CKE
A12
A12
CS#
CS#
18
17
Address
Address
register
register
Mode registers
Mode registers
Control
Control
logic
logic
17
18
14
counter
15
Refresh
Refresh
counter
ZQCL, ZQCS
ZQCL, ZQCS
10
10
3
3
BC4 (burst chop)
OTF
BC4 (burst chop)
OTF
13
15
address
3
3
address
Row-
MUX
Row-
MUX
Column-
counter/
control
address
Column-
counter/
address
control
14
Bank
logic
latch
Bank
15
latch
logic
ZQ CAL
ZQ CAL
decoder
address
Bank 0
decoder
row-
latch
address
Bank 0
and
latch
row-
Bank 1
and
Bank 1
Bank 2
7
3
Bank 2
7
3
Bank 3
Bank 3
Bank 4
16,384
Bank 4
32,768
Bank 5
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 6
Columns 0, 1, and 2
Bank 7
Bank 7
(16,384 x 128 x 128)
To ODT/output drivers
Sense amplifiers
(32,768 x 128 x 64)
To ODT/output drivers
DM mask logic
Sense amplifiers
DM mask logic
I/O gating
I/O gating
memory
Column
decoder
decoder
Bank 0
16,384
x128)
Memory
Column
array
(128
Bank 0
8,192
Bank 1
array
(128
x64)
Bank 1
Bank 2
Bank 2
Bank 3
Bank 3
Bank 4
Bank 4
Bank 5
Bank 5
Bank 6
Bank 6
Bank 7
15
Bank 7
128
BC4
OTF
64
BC4
OTF
128
128
Micron Technology, Inc. reserves the right to change products or specifications without notice.
64
64
Column 0, 1, and 2
Columns 0, 1, and 2
interface
CK, CK#
Data
interface
READ
MUX
FIFO
data
READ
CK, CK#
and
MUX
FIFO
data
and
Data
2Gb: x4, x8, x16 DDR3 SDRAM
Data
Data
16
lower nibble for BC4)
16
8
8
lower nibble for BC4)
(select upper or
(select upper or
Functional Block Diagrams
Column 2
drivers
WRITE
input
logic
Column 2
and
drivers
Write
input
logic
control
and
ODT
control
CK, CK#
ODT
drivers
READ
CK, CK#
drivers
DLL
BC4
Read
DLL
BC4
DQ[15:0]
© 2006 Micron Technology, Inc. All rights reserved.
LDQS, LDQS#, UDQS, UDQS#
DQS, DQS#
sw1
sw1
sw1
DQ[7:0]
sw1
sw1
sw1
R
R
R
V
TT,nom
R
R
V
TT,nom
V
TT,nom
R
V
DDQ
V
V
TT,nom
DDQ
DDQ
TT,nom
TT,nom
DDQ
DDQ
DDQ
/2
/2
/2
/2
/2
/2
DQ8
R
R
R
sw2
R
TT(WR)
sw2
sw2
R
TT(WR)
sw2
R
TT(WR)
TT(WR)
TT(WR)
TT(WR)
sw2
sw2
(1 . . . 4)
(1, 2)
(1 . . . 16)
(1, 2)
(1 . . . 8)
LDM/UDM
DQ[15:0]
LDQS, LDQS#
UDQS, UDQS#
TDQS#
DQS/DQS#
DM/TDQS
(shared pin)
DQ[7:0]