Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet

ADAPTER ICE Z8 ENCORE 64K 64LQFP

Z8F64220100ZDA

Manufacturer Part Number
Z8F64220100ZDA
Description
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Manufacturer
Zilog
Datasheets

Specifications of Z8F64220100ZDA

Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3403
High Performance 8-Bit Microcontrollers
®
Z8 Encore! XP
F64XX Series
Product Specification
PS019921-0308
®
Copyright ©2008 by Zilog
, Inc. All rights reserved.
www.zilog.com

Z8F64220100ZDA Summary of contents

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... High Performance 8-Bit Microcontrollers Z8 Encore! XP Product Specification PS019921-0308 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ® F64XX Series ...

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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS019921-0308 ...

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... Added ZENETSC0100ZACG to the end of the Ordering Information table. Changed the flag status to unaffected for BIT, BSET, and BCLR in Table 133 on page 246. Updated Zilog logo, Disclaimer section, and implemented style guide. Updated Changed Z8 Encore! 64K Series to Z8 Encore! XP 64K Series Flash Microcontrollers throughout the document ...

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Table of Contents Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 External Driver Enable . . . ...

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Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Therefore, we have designed this product specification to be used either as a how to procedural manual or a reference guide to important data. Intended Audience This document is written for Zilog customers who are experienced at working with micro- controllers, integrated circuits, or printed circuit assemblies. Manual Conventions The following assumptions and conventions are adopted to provide clarity and ease of use: ...

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Braces The curly braces indicate a single register or bus created by concatenating some combination of smaller registers, buses, or individual bits. • Example: The 12-bit register address { hexadecimal value ( (RP) and Working Register R1. 12-bit ...

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Use of All Uppercase Letters The use of all uppercase letters designates the names of states, modes, and commands. • Example 1: The bus is considered BUSY after the Start condition. • Example 2: A START command triggers the processing ...

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... Introduction Zilog’s Z8 Encore! XP MCU family of products are a line of Zilog products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP referred to collectively as the Z8 Encore the F64XX Series adds Flash memory to Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new ™ ...

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... F64XX Series Part Selection Guide Part Flash RAM Number (KB) (KB) I/O Z8F1621 Z8F1622 Z8F2421 Z8F2422 Z8F3221 Z8F3222 Z8F4821 Z8F4822 Z8F4823 Z8F6421 Z8F6422 Z8F6423 Die Form Contact ® Sales Zilog PS019921-0308 16-bit Timers ADC UARTs 2 with PWM Inputs with IrDA I C SPI ® ...

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Block Diagram Figure 1 displays the block diagram of the architecture of the Z8 Encore! XP Series. XTAL/RC Oscillator System Clock Memory Busses Register Bus Timers UARTs IrDA Figure 1. Z8 Encore! XP CPU and Peripheral Overview ™ eZ8 CPU ...

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... C-Compiler friendly • clock cycles per instruction For more information on the eZ8 CPU, refer to eZ8 available for download at www.zilog.com. General-Purpose Input/Output The Z8 Encore! XP port (Port H) for general-purpose input/output (GPIO). Each pin is individually programmable. All ports (except B and H) support 5 V-tolerant inputs. ...

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The I C controller makes the Z8 Encore! XP compatible with the I controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line. Serial Peripheral Interface The serial ...

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PS019921-0308 ® Z8 Encore! XP F64XX Series Product Specification Introduction 6 ...

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Signal and Pin Descriptions The Z8 Encore! XP and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information on physical package specifications, see Packaging on page 261. Available Packages Table ...

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Pin Configurations Figure 2 through available in the Z8 Encore! XP F64XX Series. For description of the signals, see on page 13. Timer 3 is not available in the 44-pin packages. PA0 / T0IN PD2 PC2 / SS RESET VDD ...

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PA0 / T0IN PD2 PC2 / SS RESET VDD VSS PD1 PD0 XOUT XIN VDD Figure 3. Z8 Encore! XP F64XX Series in 44-Pin Low-Profile Quad Flat Package (LQFP) PS019921-0308 ® ...

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PA0 / T0IN 49 PD2 PC2 / SS RESET VDD PE4 PE3 VSS 56 PE2 PE1 PE0 VSS PD1 / T3OUT PD0 / T3IN XOUT XIN 64 1 Figure 4. Z8 Encore! XP F64XX Series in 64-Pin Low-Profile Quad ...

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PA0 / T0IN 10 PD2 PC2 / SS RESET VDD PE4 PE3 VSS 18 PE2 PE1 PE0 VSS VDD PD1 / T3OUT PD0 / T3IN XOUT XIN 26 27 Figure 5. Z8 Encore! XP F64XX Series in 68-Pin Plastic ...

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PA0 / T0IN 1 PD2 PC2 / SS PF6 RESET 5 VDD PF5 PF4 PF3 10 PE4 PE3 VSS PE2 PE1 15 PE0 VSS PF2 PF1 PF0 20 VDD PD1 / T3OUT PD0 / T3IN XOUT 24 XIN 25 ...

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Signal Descriptions Table 3 describes the Z8 Encore! XP signals. To determine the signals available for the specific package styles, see Table 3. Signal Descriptions Signal Mnemonic I/O Description General-Purpose I/O Ports A-H PA[7:0] I/O Port A[7:0]. These pins are ...

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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description SCK I/O SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! XP F64XX Series is the SPI master, this pin is an output. If the Z8 Encore! ...

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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the signal is usable with external RC networks and ...

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Table 4. Pin Characteristics of the Z8 Encore! XP F64XX Series Symbol Reset Mnemonic Direction Direction AVSS N/A N/A AVDD N/A N/A DBG I/O I VSS N/A N/A PA[7:0] I/O I PB[7:0] I/O I PC[7:0] I/O I PD[7:0] I/O I ...

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... These three address spaces are covered briefly in the following subsections. For more information on eZ8 CPU and its address space, refer to eZ8 (UM0128) available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! XP F64XX Series (4096 bytes). The Register File is composed of two sections—control registers and general-purpose reg- isters ...

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Flash memory addresses returns Memory addresses produces no effect. the Z8 Encore! XP F64XX Series products. Table 5. Z8 Encore! XP F64XX Series Program Memory Maps Program Memory Address (Hex) Function Z8F162x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-3FFF ...

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Table 5. Z8 Encore! XP F64XX Series Program Memory Maps (Continued) Program Memory Address (Hex) Function 0008-0037 0038-BFFF Z8F642x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-FFFF *See Table 23 on page 63 for a list of the interrupt vectors. Data ...

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Table 6. Z8 Encore! XP F64XX Series Information Area Map Program Memory Address (Hex) FE00H-FE3FH FE40H-FE53H FE54H-FFFFH PS019921-0308 Z8 Encore! XP Function Reserved Part Number 20-character ASCII alphanumeric code Left justified and filled with zeros (ASCII Null character) Reserved ® ...

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Register File Address Map Table 7 provides the address map for the Register File of the Z8 Encore! XP F64XX Series products. Not all devices and package styles in the Z8 Encore! XP F64XX Series support Timer 3 and all ...

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Table 7. Z8 Encore! XP F64XX Series Register File Address Map (Continued) Address (Hex) Register Description F17 Timer 2 Control 1 Timer 3 (unavailable in the 44-pin packages) F18 Timer 3 High Byte F19 Timer 3 Low Byte F1A Timer ...

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Table 7. Z8 Encore! XP F64XX Series Register File Address Map (Continued) Address (Hex) Register Description F60 SPI Data F61 SPI Control F62 SPI Status F63 SPI Mode F64 SPI Diagnostic State F65 Reserved F66 SPI Baud Rate High Byte ...

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Table 7. Z8 Encore! XP F64XX Series Register File Address Map (Continued) Address (Hex) Register Description FC9-FCC Reserved FCD Interrupt Edge Select FCE Interrupt Port Select FCF Interrupt Control GPIO Port A FD0 Port A Address FD1 Port A Control ...

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Table 7. Z8 Encore! XP F64XX Series Register File Address Map (Continued) Address (Hex) Register Description FEE Port H Input Data FEF Port H Output Data Watchdog Timer FF0 Watchdog Timer Control FF1 Watchdog Timer Reload Upper Byte FF2 Watchdog ...

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Control Register Summary Timer 0 High Byte T0H (F00H - Read/Write Timer 0 current count value [15:8] Timer 0 Low Byte T0L (F01H - Read/Write ...

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Timer 1 PWM High Byte T1PWMH (F0CH - Read/Write Timer 1 PWM value [15:8] Timer 1 PWM Low Byte T1PWML (F0DH - Read/Write Timer ...

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Timer 2 Control 1 T2CTL1 (F17H - Read/Write Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = ...

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UART0 Transmit Data U0TXD (F40H - Write Only UART0 transmitter data byte [7:0] UART0 Receive Data U0RXD (F40H - Read Only UART0 receiver data ...

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UART0 Control 1 U0CTL1 (F43H - Read/Write Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors ...

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UART1 Status 0 U1STAT0 (F49H - Read Only CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data ...

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UART1 Control 1 U0CTL1 (F4BH - Read/Write Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors ...

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I C Status I2CSTAT (F51H - Read Only NACK Interrupt action required to service NAK 1 = START/STOP not set after NAK Data Shift State 0 = Data ...

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SPI Data SPIDATA (F60H - Read/Write SPI Data [7:0] SPI Control SPICTL (F61H - Read/Write SPI Enable 0 = SPI disabled 1 = SPI ...

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SPI Mode SPIMODE (F63H - Read/Write 111 = 7 bits Diagnostic Mode Control 0 = Reading from SPIBRH, SPIBRL returns reload values 1 = Reading from SPIBRH, SPIBRL returns current BRG count ...

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DMA0 Control DMA0CTL (FB0H - Read/Write Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Received Data register ...

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DMA1 Control DMA1CTL (FB8H - Read/Write Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Transmit Data register ...

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DMA_ADC Control DMAACTL (FBEH - Read/Write ADC Analog Input Number 0000 = Analog input 0 updated 0001 = Analog input 0-1 updated 0010 = Analog input 0-2 updated 0011 = Analog input ...

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IRQ0 Enable Low Bit IRQ0ENL (FC2H - Read/Write ADC IRQ Enable Hit Bit SPI IRQ Enable Low Bit I2C IRQ Enable Low Bit UART 0 Transmitter IRQ Enable UART 0 Receiver IRQ ...

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Interrupt Port Select IRQPS (FCEH - Read/Write Port Port Pin Select [7: Port A pin is the interrupt source 1 = Port D pin is the interrupt ...

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Port C Control PCCTL (FD9H - Read/Write Port C Control[7:0] Provides Access to Port Sub- Registers Port C Input Data PCIN (FDAH - Read Only ...

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Port F Control PFCTL (FE5H - Read/Write Port F Control[7:0] Provides Access to Port Sub- Registers Port F Input Data PFIN (FE6H - Read Only ...

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Watchdog Timer Control WDTCTL (FF0H - Read Only Configuration Indicator Reserved EXT 0 = Reset not generated by RESET pin 1 = Reset generated by RESET pin WDT 0 = WDT ...

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Flags FLAGS (FFC - Read/Write User Flag User Flag Half Carry D - Decimal Adjust V - Overflow Flag S - Sign Flag Z ...

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Reset and Stop Mode Recovery The Reset Controller within the Z8 Encore! XP F64XX Series controls Reset and Stop Mode Recovery operation. In typical operation, the following events cause a Reset to occur: • Power-On Reset • Voltage Brownout • ...

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System Reset During a system reset, the Z8 Encore! XP F64XX Series devices are held in Reset for 66 cycles of the Watchdog Timer oscillator followed by 16 cycles of the system clock. At the beginning of Reset, all GPIO ...

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Power-On Reset Each device in the Z8 Encore! XP F64XX Series contains an internal Power-On Reset cir- cuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe ...

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VBO threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (V block holds the device in the Reset state. After the supply voltage again exceeds the ...

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WDT_RES Option Bit. The Control register is set to signify that the reset was initiated by the Watchdog Timer. External Pin Reset The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and ...

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Table 10. Stop Mode Recovery Sources and Resulting Action Operating Mode Stop Mode Recovery Source STOP mode Watchdog Timer time-out when configured for Reset Watchdog Timer time-out when configured for interrupt Data transition on any GPIO Port pin enabled as ...

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Low-Power Modes The Z8 Encore! XP F64XX Series products contain power-saving features. The highest level of power reduction is provided by STOP mode. The next level of power reduction is provided by the HALT mode. STOP Mode Execution of the ...

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Program Counter stops incrementing. • Watchdog Timer’s internal RC oscillator continues to operate. • The Watchdog Timer continues to operate, if enabled. • All other on-chip peripherals continue to operate. The eZ8 CPU can be brought out of HALT ...

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General-Purpose I/O The Z8 Encore! XP F64XX Series products support a maximum of seven 8-bit ports (Ports A–G) and one 4-bit port (Port H) for general-purpose input/output (GPIO) operations. Each port consists of control and data registers. The GPIO control ...

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System Port Output Data Register DATA D Q Bus System Clock Figure 9. GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used as both general-purpose I/O and to provide access to on-chip ...

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Table 12. Port Alternate Function Mapping Port Pin Port A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Port B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PS019921-0308 Mnemonic ...

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Table 12. Port Alternate Function Mapping (Continued) Port Pin Port D PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Port E PE[7:0] N/A Port F PF[7:0] N/A Port G PG[7:0] N/A Port H PH0 PH1 PH2 PH3 GPIO Interrupts Many ...

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Table 13. GPIO Port Registers and Sub-Registers Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Sub-Register Mnemonic Port Register Name PxDD PxAF PxOC PxDD PxSMRE Port A–H Address Registers The Port A–H Address registers select the GPIO Port functionality accessible ...

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PADDR[7:0]—Port Address The Port Address selects one of the sub-registers accessible through the Port Control reg- ister. PADDR[7:0] 00H 01H 02H 03H 04H 05H 06H-FFH Port A–H Control Registers The Port A–H Control registers set the GPIO port operation. The ...

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Port A H Data Direction Sub-Registers The Port A–H Data Direction sub-register is accessed through the Port A–H Control regis- ter by writing 01H to the Port A–H Address register Table 16. Port A–H Data Direction Sub-Registers BITS 7 ...

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AF[7:0]—Port Alternate Function enabled 0 = The port pin is in NORMAL mode and the DDx bit in the Port A–H Data Direction sub-register determines the direction of the pin The alternate function is selected. Port pin operation ...

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Table 19. Port A–H High Drive Enable Sub-Registers BITS 7 6 PHDE7 PHDE6 FIELD RESET R/W If 04H in Port A-H Address Register, accessible through Port A-H Control Register ADDR PHDE[7:0]—Port High Drive Enabled 0 = The Port pin is ...

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Port A–H Input Data Registers Reading from the Port A–H Input Data registers from the corresponding port pins. The Port A–H Input Data registers are Read-only. Table 21. Port A–H Input Data Registers (PxIN) BITS 7 6 PIN7 PIN6 FIELD ...

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... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. For more information on interrupt servicing by the eZ8 CPU, refer to eZ8 download at www.zilog.com. Interrupt Vector Listing Table 23 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most-significant byte (MSB) at the even Program Memory address and the least-significant byte (LSB) at the following odd Program Memory address ...

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Table 23. Interrupt Vectors in Order of Priority (Continued) (Continued) Program Memory Priority Vector Address 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H Lowest 0036H Architecture ...

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Port Interrupts Internal Interrupts Figure 10. Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: ...

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Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts were enabled ...

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LDX command and the last LDX command are lost. Poor coding style that can result in lost interrupt requests: To avoid missing interrupts, the following style of coding to set bits in ...

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T1I—Timer 1 Interrupt Request interrupt request is pending for Timer interrupt request from Timer 1 is awaiting service. T0I—Timer 0 Interrupt Request interrupt request is pending for Timer 0. 1 ...

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PADxI—Port A or Port D Pin x Interrupt Request interrupt request is pending for GPIO Port A or Port D pin interrupt request from GPIO Port A or Port D pin x is ...

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GPIO Port C pin number (0 through 3). IRQ0 Enable High and Low Bit Registers The IRQ0 Enable High and Low Bit registers (see a priority encoded enabling for interrupts in the Interrupt Request 0 ...

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Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) BITS 7 6 T2ENL T1ENL FIELD RESET R/W ADDR T2ENL—Timer 2 Interrupt Request Enable Low Bit T1ENL—Timer 1 Interrupt Request Enable Low Bit T0ENL—Timer 0 Interrupt Request Enable Low Bit U0RENL—UART 0 ...

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Table 31. IRQ1 Enable High Bit Register (IRQ1ENH) BITS 7 6 PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH FIELD 0 0 RESET R/W R/W R/W ADDR PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit. For selection ...

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Table 33. IRQ2 Enable and Priority Encoding (Continued) IRQ2ENH[x] IRQ2ENL[x] 1 Note: where x indicates the register bits from 0 through 7. Table 34. IRQ2 Enable High Bit Register (IRQ2ENH) BITS 7 6 T3ENH U1RENH FIELD RESET R/W ADDR T3ENH—Timer ...

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C1ENL—Port C1 Interrupt Request Enable Low Bit C0ENL—Port C0 Interrupt Request Enable Low Bit Interrupt Edge Select Register The Interrupt Edge Select (IRQES) register generated for the rising edge or falling edge on the selected GPIO Port input pin. The ...

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PADxS—PAx/PDx Selection 0 = PAx is used for the interrupt for PAx/PDx interrupt request PDx is used for the interrupt for PAx/PDx interrupt request. where x indicates the specific GPIO Port pin number (0 through 7). Interrupt Control ...

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PS019921-0308 ® Z8 Encore! XP F64XX Series Product Specification Interrupt Controller 76 ...

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Timers The Z8 Encore! XP that can be used for timing, event counting, or generation of pulse width modulated sig- nals. The timers’ features include: • 16-bit reload counter • Programmable prescaler with prescale values from 1 to 128 • ...

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Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the Timer Reload High and Low Byte registers and setting the prescale ...

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One-Shot time-out, first set the TPOL bit in the Timer Control 1 Register to the start value before beginning ONE-SHOT mode. Then, after starting the timer, set TPOL to the oppo- site bit value. Follow the steps below for configuring ...

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Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H), affecting only the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset ...

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Select either the rising edge or falling edge of the Timer Input signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function does not ...

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Follow the steps below for configuring a timer for PWM mode and initiating the PWM operation: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for PWM mode – Set the prescale ...

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The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt and continues counting. Follow the steps below for configuring a ...

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Follow the steps below for configuring a timer for COMPARE mode and initiating the count: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for COMPARE mode – Set the prescale value ...

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Set the prescale value 2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always ...

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Write to the Timer Control 1 register to enable the timer. 7. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In m/COMPARE mode, the elapsed time from ...

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Table 39. Timer 0-3 High Byte Register (TxH) BITS 7 6 FIELD RESET R/W ADDR Table 40. Timer 0-3 Low Byte Register (TxL) BITS 7 6 FIELD RESET R/W ADDR TH and TL—Timer High and Low Bytes These 2 bytes, ...

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Table 42. Timer 0-3 Reload Low Byte Register (TxRL) BITS 7 6 FIELD RESET R/W ADDR TRH and TRL—Timer Reload Register High and Low These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the maximum count ...

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PWMH and PWML—Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. When a match occurs, the PWM output changes state. The PWM output value is ...

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Timer 0-3 Control 1 Registers The Timer 0-3 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode. Table 46. Timer 0-3 Control 1 Register (TxCTL1) BITS 7 6 TEN TPOL FIELD RESET ...

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Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on ...

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Divide by 64 111 = Divide by 128 TMODE—TIMER mode 000 = ONE-SHOT mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode ...

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Watchdog Timer The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore! XP into unsuit- able operating states. The features of Watchdog Timer include: • On-chip RC ...

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Table 47. Watchdog Timer Approximate Time-Out Delays WDT Reload Value WDT Reload Value (Hex) (Decimal) 000004 FFFFFF 16,777,215 Watchdog Timer Refresh When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers. The Watchdog ...

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STOP mode. For more information on Stop Mode Recovery, see Recovery on page 45. If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector ...

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Write to the Watchdog Timer Control register (WDTCTL). AAH 3. Write the Watchdog Timer Reload Upper Byte register (WDTU). 4. Write the Watchdog Timer Reload High Byte register (WDTH). 5. Write the Watchdog Timer Reload Low Byte register (WDTL). ...

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Reset or Stop Mode Recovery Event Power-On Reset Reset using RESET pin assertion Reset using Watchdog Timer time-out Reset using the On-Chip Debugger (OCDCTL[1] set Reset from STOP Mode using DBG Pin driven Low Stop Mode Recovery ...

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Caution: The 24-bit WDT Reload Value must not be set to a value less than Table 49. Watchdog Timer Reload Upper Byte Register (WDTU) BITS 7 6 FIELD RESET R/W ADDR Note: R/W* - Read returns the current WDT count ...

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UART The Universal Asynchronous Receiver/Transmitter (UART full-duplex communica- tion channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include: • 8-bit asynchronous data transfer • ...

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Parity Checker RXD Receive Shifter Receive Data Register System Bus Transmit Data Register Transmit Shift TXD Register Parity Generator CTS DE Operation Data Format The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An ...

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Idle State of Line lsb 1 Start Bit0 0 Figure 13. UART Asynchronous Data Format without Parity Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 14. UART Asynchronous Data Format with Parity Transmitting Data using the Polled ...

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Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin. 5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty ...

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Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt ...

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Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error con- ditions). Follow the steps below to configure the UART receiver for interrupt-driven oper- ation: 1. Write to the UART ...

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Clear the UART Receiver interrupt in the applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and await more data. Clear To Send (CTS) Operation The CTS pin, if enabled by the CTSE ...

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In general, the address compare feature reduces the load on the CPU, since it does not need to access the UART when it receives data directed to other devices on the multi-node network. The following three MULTIPROCESSOR modes ...

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UART Transmit Data register. The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the Start bit is transmitted. This timing allows a ...

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Receiver Interrupts The receiver generates an interrupt when any of the following occurs: • A data byte has been received and is available in the UART Receive Data register. This interrupt can be disabled independent of the other receiver interrupt ...

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Read Data Figure 17. UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the Baud Rate Generator interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This action allows the Baud ...

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UART. The UART data rate is calculated using the following equation: UART Data Rate (bits/s) When the UART is disabled, the Baud Rate Generator can function as a basic ...

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TXD—Transmit Data UART transmitter data byte to be shifted out through the TXDx pin. UART Receive Data Register Data bytes received through the RXDx pin are stored in the UART Receive Data register (Table 53). The Read-only UART Receive Data ...

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PE—Parity Error This bit indicates that a parity error has occurred. Reading the UART Receive Data regis- ter clears this bit parity error occurred parity error occurred. OE—Overrun Error This bit indicates that an ...

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Table 55. UART Status 1 Register (UxSTAT1) BITS 7 6 FIELD RESET R/W ADDR Reserved—Must be 0. NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive Data register resets this bit The ...

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REN—Receive Enable This bit enables or disables the receiver Receiver disabled Receiver enabled. CTSE—CTS Enable 0 = The CTS signal has no effect on the transmitter The UART recognizes the CTS signal as an ...

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The UART generates an interrupt request only on received address bytes The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data ...

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Infrared Encoder/Decoder is enabled. The UART transmits and receives data through the Infrared Encoder/Decoder. UART Address Compare Register The UART Address Compare register the UART. When the MPMD[1] bit of UART Control Register 0 is set, all incoming ...

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Table 59. UART Baud Rate High Byte Register (UxBRH) BITS 7 6 FIELD RESET R/W ADDR Table 60. UART Baud Rate Low Byte Register (UxBRL) BITS 7 6 FIELD RESET R/W ADDR For a given UART data rate, the integer ...

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Table 61. UART Baud Rates 20.0 MHz System Clock Desired Rate BRG Divisor Actual Rate Error (kHz) (Decimal) 1250.0 1 625.0 2 250.0 5 115.2 11 57.6 22 38.4 33 19.2 65 9.60 130 4.80 260 2.40 521 1.20 1042 ...

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Table 61. UART Baud Rates (Continued) 1.20 868 0.60 1736 0.30 3472 10.0 MHz System Clock Desired Rate BRG Divisor Actual Rate Error (kHz) (Decimal) 1250.0 N/A 625.0 1 250.0 3 115.2 5 57.6 11 38.4 16 19.2 33 9.60 ...

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Table 61. UART Baud Rates (Continued) 9.60 23 4.80 47 2.40 93 1.20 186 0.60 373 0.30 746 PS019921-0308 9.73 1.32 9.60 4.76 -0.83 4.80 2.41 0.23 2.40 1.20 0.23 1.20 0.60 -0.04 0.60 0.30 -0.04 0.30 ® Z8 Encore! ...

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... UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. PS019921-0308 ® F64XX Series products contain two fully-functional, high-perfor- RxD Infrared TxD Encoder/Decoder Baud Rate (Endec) Clock ® Z8 Encore! XP F64XX Series Product Specification ® Zilog ZHX1810 RXD RXD TXD TXD Infrared Transceiver Infrared Encoder/Decoder 121 ...

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The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to ...

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When the Infrared Endec is enabled, the UART’s RXD signal is internal to the Z8 Encore! ® XP F64XX Series products while the IR_RXD signal is received through the 16-clock period Baud Rate Clock Start Bit = 0 Data Bit ...

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Infrared Encoder/Decoder Control Register Definitions All Infrared Endec configuration and status information is set by the UART control regis- ters as defined in Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the UARTx Control ...

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Serial Peripheral Interface The Serial Peripheral Interface is a synchronous interface allowing several SPI-type devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-to- Digital Converters, and ISDN devices. Features of the SPI include: • Full-duplex, synchronous, character-oriented communication • Four-wire ...

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To Slave #2’s SS Pin To Slave #1’s SS Pin From Slave To Slave To Slave Figure 22. SPI Configured as a Master in a Single Master, Multiple Slave System From Master To Master From Master From Master Figure 23. ...

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During an SPI transfer, data is sent and received simultaneously by both the Master and the Slave SPI devices. Separate signals are required for data and the serial clock. When an SPI transfer occurs, a multi-bit (typically 8-bit) character is ...

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The Master and Slave are each capable of exchanging a character of data during a sequence of NUMBITS clock cycles (see NUMBITS field in the page 136). In both Master and Slave SPI devices, data is shifted on one edge ...

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Transfer Format PHASE Equals Zero Figure 24 displays the timing diagram for an SPI transfer in which PHASE is cleared to 0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to one. The ...

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SCK (CLKPOL = 0) SCK (CLKPOL = 1) MOSI MISO Input Sample Time SS Figure 25. SPI Timing When PHASE is 1 Multi-Master Operation In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied ...

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The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUM- BITS field in the SPIMODE register must be set to be consistent with the other SPI devices. The STR bit in the SPICTL register may be ...

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NUMBITS field in the SPI Mode register. In slave mode it is not necessary for SS to deassert between characters to generate the interrupt. The SPI in Slave mode can also ...

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SPI Control Register Definitions SPI Data Register The SPI Data register (receive) data. Reads from the SPI Data register always return the current contents of the 8-bit shift register. Data is shifted out starting with bit 7. The last bit ...

Page 148

Table 64. SPI Control Register (SPICTL) BITS 7 6 IRQE STR FIELD RESET R/W ADDR IRQE—Interrupt Request Enable 0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller SPI interrupts are enabled. Interrupt ...

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SPI Status Register The SPI Status register their reset state if the SPIEN bit in the SPICTL register = 0. Table 65. SPI Status Register (SPISTAT) BITS 7 6 IRQ OVR FIELD RESET R/W* R/W ADDR Note: R/W* = Read ...

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SS input pin is asserted (Low input is not asserted (High). If SPI enabled as a Master, this bit is not applicable. SPI Mode Register The SPI Mode register value of the SS pin. Table ...

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SSIO—Slave Select I pin configured as an input pin configured as an output (Master mode only). SSV—Slave Select Value If SSIO = 1 and SPI configured as a Master pin driven ...

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SPI Baud Rate High and Low Byte Registers The SPI Baud Rate High and Low Byte registers a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. When configured as a general purpose timer, the SPI BRG interrupt interval ...

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I C Controller 2 The I C Controller makes the Z8 Encore with the I C protocol. The I data signal (SDA) and a serial clock signal (SCL). Features of the I • Transmit and Receive Operation ...

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Architecture Figure 26 displays the architecture of the Interrupt Operation 2 The I C Controller operates in MASTER mode to transmit and receive data. Only a single master is supported. Arbitration between two masters must be ...

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Master receives from a 7-bit slave • Master receives from a 10-bit slave SDA and SCL Signals sends all addresses, data and acknowledge signals over the SDA line, most-significant bit first. SCL is the common clock ...

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Transmit interrupts occur when the TDRE bit of the I 2 bit in the I C Control register is set. Transmit interrupts occur under the following condi- tions when the transmit data register is empty: 2 • The I C ...

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In order for a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and receive the last (nth) ...

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I C Data register. Once the I next data byte. Address Only Transaction with a 7-bit Address In the situation where software determines if a slave with a 7-bit address is responding without sending or receiving data, ...

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Write Transaction with a 7-Bit Address Figure 28 displays the data transfer format for a 7-bit addressed slave. Shaded regions indicate data transferred from the I data transferred from the slaves to the I S Slave Address Figure 28. 7-Bit ...

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The I C Controller shifts the data out of using the SDA signal. After the first bit is sent, the Transmit interrupt is asserted. 14. If more bytes remain to be sent, return to 15. Software responds by ...

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The I C Controller loads the I register. 8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is asserted. 9. Software responds by writing the second byte of address into the ...

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The first seven bits transmitted in the first byte are most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the read/write control bit (=0). The transmit operation is carried out in the same manner ...

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If the I C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL, the I Continue with If the slave does not acknowledge the second address byte or one of ...

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The I C Controller sends the START condition The I C Controller shifts the address and read bit out the SDA signal the I C slave acknowledges the address by pulling the SDA ...

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Follow the steps below for the data transfer for a read operation to a 10-bit addressed slave: 1. Software writes Data register. 2. Software asserts the START and TXI bits of the The I C Controller sends ...

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The I C Controller sends the repeated START condition. 2 16. The I C Controller loads the I register (third address transfer). 2 17. The I C Controller sends slave read address and a 1 (read). 2 18. ...

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Table 70 Data Register (I2CDATA) BITS 7 6 FIELD RESET R/W ADDR Status Register The Read-only I 2 Table 71 Status Register (I2CSTAT) BITS 7 6 TDRE RDRF FIELD 1 RESET R/W ...

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Caution: Software must be cautious in making decisions based on this bit within a trans- action because software cannot tell when the bit is updated by hardware. In the case of write transactions, the I cycle if the next transmit ...

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IEN—I C Enable The I C transmitter and receiver are enabled The I C transmitter and receiver are disabled. START—Send Start Condition This bit sends the Start condition. Once asserted cleared ...

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I C Baud Rate High and Low Byte Registers 2 The I C Baud Rate High and Low Byte registers (Tables 73 and 73) combine to form a 16-bit reload value, BRG[15:0], for the I 2 When the I ...

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Table 74 Baud Rate Low Byte Register (I2CBRL) BITS 7 6 FIELD RESET R/W ADDR 2 BRL = I C Baud Rate Low Byte Least significant byte, BRG[7:0], of the I Note: If the DIAG bit in ...

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TXRXSTATE 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 0_1000 0_1001 0_1010 0_1011 0_1100 0_1101 0_1110 0_1111 1_0000 1_0001 1_0010 1_0011 1_0100 1_0101 1_0110 1_0111 1_1000 1_1001 1_1010 1_1011 1_1100 PS019921-0308 State Description Idle State START State Send/Receive data bit ...

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TXRXSTATE 1_1101 1_1110 1_1111 2 C Diagnostic Control Register I 2 The I C Diagnostic register ter is a read/write register used for I 2 Table 76 Diagnostic Control Register (I2CDIAG) BITS 7 6 FIELD RESET R/W ADDR ...

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PS019921-0308 ® Z8 Encore! XP F64XX Series Product Specification I2C Controller 160 ...

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Direct Memory Access Controller The Z8 Encore! XP three independent Direct Memory Access channels. Two of the channels (DMA0 and DMA1) transfer data between the on-chip peripherals and the Register File. The third channel (DMA_ADC) controls the ADC operation and ...

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Write the Start and End Register File address high nibbles to the DMAx End/Start Address High Nibble register. 4. Write the lower byte of the Start Address to the DMAx Start/Current Address register. 5. Write the lower byte of ...

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Enable the DMA_ADC interrupt request, if desired – Select the number of ADC Analog Inputs to convert – Enable the DMA_ADC channel Caution: When using the DMA_ADC to perform conversions on multiple ADC inputs, the Analog-to-Digital Converter must be ...

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DMAx, after the End Address data is transferred, reloads the original Start Address and continues operating. DDIR—DMAx Data Transfer Direction 0 = Register File → on-chip peripheral control register on-chip peripheral control register → Register File. ...

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DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the DMAx I/O Address register must contain an even numbered address. Table 78. DMAx I/O Address Register (DMAxIO) BITS 7 6 FIELD RESET R/W ADDR DMA_IO—DMA on-chip peripheral control register ...

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DMAx Start/Current Address Low Byte Register The DMAx Start/Current Address Low register, in conjunction with the DMAx Address High Nibble register, forms a 12-bit Start/Current Address. Writes to this register set the Start Address for DMA operations. Each time the ...

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DMA_ADC Address Register The DMA_ADC Address register ADC conversion values as displayed in significant bits of the 12-bit Register File addresses. The five least-significant bits are cal- culated from the ADC Analog Input number (5-bit base address is equal to ...

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DMAA_ADDR—DMA_ADC Address These bits specify the seven most-significant bits of the 12-bit Register File addresses used for storing the ADC output data. The ADC Analog Input Number defines the five least-significant bits of the Register File address. Full 12-bit address ...

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ADC Analog Inputs 0-5 updated. 0110 = ADC Analog Inputs 0-6 updated. 0111 = ADC Analog Inputs 0-7 updated. 1000 = ADC Analog Inputs 0-8 updated. 1001 = ADC Analog Inputs 0-9 updated. 1010 = ADC Analog Inputs ...

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DMA0 is not the source of the interrupt from the DMA Controller DMA0 completed transfer of data to/from the End Address and generated an interrupt. PS019921-0308 ® Z8 Encore! XP F64XX Series Product Specification Direct Memory ...

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Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The features of the sigma-delta ADC include: • 12 analog input sources are multiplexed with general-purpose I/O ports • Interrupt upon conversion complete • ...

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Internal Voltage Reference Generator Analog-to-Digital Converter Reference Input Analog Input Figure 33. Analog-to-Digital Converter Block Diagram The sigma-delta ADC architecture provides alias and image attenuation below the ampli- tude resolution of the ADC in the frequency range ...

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Single-Shot Conversion When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. Follow the steps below for setting up the ADC and initiating ...

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Follow the steps below for setting up the ADC and initiating continuous conversion: 1. Enable the desired analog input by configuring the general-purpose I/O pins for alternate function. This disables the digital input and output driver. 2. Write to the ...

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ADC Control Register Definitions ADC Control Register The ADC Control register selects the analog input channel and initiates the analog-to-dig- ital conversion. Table 86. ADC Control Register (ADCCTL) BITS 7 6 CEN Reserved FIELD 0 RESET R/W ADDR CEN—Conversion Enable ...

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ANA5 0110 = ANA6 0111 = ANA7 1000 = ANA8 1001 = ANA9 1010 = ANA10 1011 = ANA11 11XX = Reserved. ADC Data High Byte Register The ADC Data High Byte register ADC output. During a single-shot ...

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Table 88. ADC Data Low Bits Register (ADCD_L) BITS 7 6 ADCD_L FIELD RESET R/W ADDR ADCD_L—ADC Data Low Bits These are the least significant two bits of the 10-bit ADC output. These bits are undefined after a Reset. Reserved ...

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PS019921-0308 ® Z8 Encore! XP F64XX Series Product Specification Analog-to-Digital Converter 178 ...

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Flash Memory The products in the Z8 Encore! XP non-volatile Flash memory with read/write/erase capability. The Flash memory can be programmed and erased in-circuit by either user code or through the On-Chip Debugger. The Flash memory array is arranged in ...

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Table 90. Flash Memory Sector Addresses Sector Number Z8F162x 0 0000H-07FFH 1 0800H-0FFFH 2 1000H-17FFH 3 1800H-1FFFH 4 2000H-27FFH 5 2800H-2FFFH 6 3000H-37FFH 7 3800H-3FFFH Figure 34. Flash Memory Arrangement PS019921-0308 Flash Sector Address Ranges Z8F242x Z8F322x 0000H-0FFFH 0000H-0FFFH 1000H-1FFFH ...

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Information Area Table 91 describes the Z8 Encore! XP Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access is enabled, the Information Area is mapped into Flash Memory and overlays the 512 ...

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Timing Using the Flash Frequency Registers Before performing a program or erase operation on the Flash memory, you must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasure of the Flash ...

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Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in Flash Sector Protection The Flash Sector Protect register can be ...

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While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Interrupts that occur when a Program- ming operation is in progress are serviced once the Programming operation is ...

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... Flash memory. For more information on bypassing the Flash Controller, refer to Third-Party Flash Pro- gramming Support for Z8 Encore! available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger: • ...

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Flash Control Register Definitions Flash Control Register The Flash Control register erase operations select the Flash Sector Protect register. The Write-only Flash Control Register shares its Register File address with the Read-only Flash Status Register. Table 92. Flash ...

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