Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 130
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 58. UART Address Compare Register (UxADDR)
UART Address Compare Register
UART Baud Rate High and Low Byte Registers
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data
The UART Address Compare register
the UART. When the MPMD bit of UART Control Register 0 is set, all incoming
address bytes are compared to the value stored in the Address Compare register. Receive
interrupts and RDA assertions only occur in the event of a match.
This 8-bit value is compared to the incoming address bytes.
The UART Baud Rate High and Low Byte registers (see
page 117) combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data
transmission rate (baud rate) of the UART. To configure the Baud Rate Generator as a
timer with interrupt on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
When configured as a general purpose timer, the UART BRG interrupt interval is calcu-
lated using the following equation:
BRGCTL bit in the UART Control 1 register to 1.
through the Infrared Encoder/Decoder.
UART BRG Interrupt Interval s ( )
F45H and F4DH
System Clock Period (s) BRG 15:0
58) stores the multi-node network address of
Z8 Encore! XP