Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 168
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 72. I
C Control Register
C Control Register (I2CCTL)
This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I
START bit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I
DSS—Data Shift State
This bit is active high while data is being shifted to or from the I
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the START or STOP bit, allowing you to specify whether to perform
a STOP or a repeated START.
action because software cannot tell when the bit is updated by hardware. In the
case of write transactions, the I
cycle if the next transmit data or address byte has not been written (TDRE = 1)
and STOP and START = 0. In this case the ACK bit is not updated until the
transmit interrupt is serviced and the Acknowledge cycle for the previous byte
completes. For examples of how the ACK bit can be used, see
Transaction with a 7-bit Address
with a 10-bit Address
Software must be cautious in making decisions based on this bit within a trans-
C Control register
on page 146.
72) enables the I
C pauses at the beginning of the Acknowledge
on page 144 and
Address Only Transaction
Z8 Encore! XP
C Shift register after the
C Shift register.
C Shift register.