Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 128
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 57. UART Control 1 Register (UxCTL1)
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is over-
ridden by the
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
F43H and F4BH
Z8 Encore! XP