CP2400DK Silicon Laboratories Inc, CP2400DK Datasheet - Page 107

• Manufacturer Part Number: CP2400DK
• Description: KIT EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400DK

• Main Purpose: LCD Development
• Embedded: Yes
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Modules
• Core Processor: C8051F930
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: C8051F930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1858; 336-1858

SFR Definition 15.1. SMBCF: SMBus Clock/Configuration
Address: 0x68
Note: This register has a reset value of 0x00 in devices that do not support SMBus.
Bit
1
7
6
5
4
3
2
(CP2400/2)
(CP2401/3)
:0
Name
Reset
Reset
Type
Bit
EXTHOLD
SMBTOE
Reserved
SMBFTE
ENSMB
Name
BUSY
INH
ENSMB
R/W
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface constantly
monitors the SDA and SCL pins.
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus.
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times.
0: Setup time is 4 system clocks and hold time is 3 system clocks.
1: Setup time is 11 system clocks and hold time is 12 system clocks.
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 0 to
reload while SCL is high and allows Timer 0 to count when SCL goes low. The Timer 0 reload
value should be set to overflow the timer after 25 ms.
SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 50 µs.
Read = 00b. Must write 00b.
7
0
1
R/W
INH
6
0
0
BUSY
R
5
0
0
Rev. 1.0
EXTHOLD SMBTOE
R/W
4
0
1
Function
R/W
3
0
1
SMBFTE
R/W
2
0
1
CP2400/1/2/3
1
0
0
Reserved
R/W
0
0
0
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